Datasheet

Timer/PWM (TPM)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 169
If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear
status flags after changing channel configuration bits and before enabling channel interrupts or using the
status flags to avoid any unexpected behavior.
10.7.5 Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel value registers are cleared
by reset.
Table 10-5. Mode, Edge, and Level Selection
CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration
XXX 00
Pin not used for TPM channel; use as an external clock for the TPM or
revert to general-purpose I/O
0
00
01
Input capture
Capture on rising edge only
10 Capture on falling edge only
11 Capture on rising or falling edge
01
00
Output compare
Software compare only
01 Toggle output on compare
10 Clear output on compare
11 Set output on compare
1X
10
Edge-aligned
PWM
High-true pulses (clear output on compare)
X1 Low-true pulses (set output on compare)
1XX
10
Center-aligned
PWM
High-true pulses (clear output on compare-up)
X1 Low-true pulses (set output on compare-up)
76543210
R
Bit 15 14 13 12 11 10 9 Bit 8
W
Reset00000000
Figure 10-11. Timer x Channel Value Register High (TPMxCnVH)
76543210
R
Bit 7654321Bit 0
W
Reset00000000
Figure 10-12. Timer Channel Value Register Low (TPMxCnVL)