Datasheet

Analog-to-Digital Converter (S08ATDV3)
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 229
• ATD input capacitance (C
AIN
– maximum value 50 pF) — This is the internal capacitance of the
ATD sample and hold circuit. This capacitance varies with temperature, voltage, and process
variation but a worst case number is necessary to compute worst case sample error.
• ATD conversion clock frequency (f
ATD CL K
– maximum value 2 MHz) — This is the frequency of
the clock input to the ATD and is dependent on the bus clock frequency and the ATD prescaler.
This frequency determines the width of the sample window, which is 14 ATDCLK cycles.
• Input sample frequency (f
SAMP
– see Appendix A, “Electrical Characteristics”) — This is the
frequency that a given input is sampled.
• Delta-input sample voltage (ΔV
SAMP
) — This is the difference between the current input voltage
(intended for conversion) and the previously sampled voltage (which may be from a different
channel). In non-continuous convert mode, this is assumed to be the greater of (V
REFH
– V
AIN
) and
(V
AIN
– V
REFL
). In continuous convert mode, 5 LSB should be added to the known difference to
account for leakage and other losses.
• Delta-analog input voltage (ΔV
AIN
) — This is the difference between the current input voltage and
the input voltage during the last conversion on a given channel. This is based on the slew rate of
the input.
In cases where there is no external filtering capacitance, the sampling error is determined by the number
of time constants of charging and the change in input voltage relative to the resolution of the ATD:
# of time constants (τ) = (14 / f
ATDCLK
) / ((R
AS
+ R
AIN
) * C
AIN
) Eqn. 14-1
sampling error in LSB (E
S
) = 2
N
* (ΔV
SAMP
/ (V
REFH
- V
REFL
)) * e
−τ
The maximum sampling error (assuming maximum change on the input voltage) will be:
E
S
= (3.6/3.6) * e
–(14/((7 k + 10 k) * 50 p * 2 M))
* 1024 = 0.271 LSB Eqn. 14-2
In the case where an external filtering capacitance is applied, the sampling error can be reduced based on
the size of the source capacitor (C
AS
) relative to the analog input capacitance (C
AIN
). Ignoring the analog
source impedance (R
AS
), C
AS
will charge C
AIN
to a value of:
E
S
= 2
N
* (ΔV
SAMP
/ (V
REFH
– V
REFL
)) * (C
AIN
/ (C
AIN
+ C
AS
)) Eqn. 14-3
In the case of a 0.1 μF C
AS
, a worst case sampling error of 0.5 LSB is achieved regardless of R
AS
.
However, in the case of repeated conversions at a rate of f
SAMP
, R
AS
must re-charge C
AS
. This recharge is
continuous and controlled only by R
AS
(not R
AIN
), and reduces the overall sampling error to:
E
S
= 2
N
* {(ΔV
AIN
/ (V
REFH
– V
REFL
)) * e
−(1 / (f
SAMP
* R
AS
* C
AS
)
+ (ΔV
SAMP
/ (V
REFH
- V
REFL
)) * Min[(C
AIN
/ (C
AIN
+ C
AS
)), e
−(1 / (f
ATDCLK
* (R
AS
+ R
AIN
) * C
AIN
)
]} Eqn. 14-4
This is a worst case sampling error which does not account for R
AS
recharging the combination of C
AS
and C
AIN
during the sample window. It does illustrate that high values of R
AS
(>10 kΩ) are possible if a
large C
AS
is used and sufficient time to recharge C
AS
is provided between samples. In order to achieve
accuracy specified under the worst case conditions of maximum ΔV
SAMP
and minimum C
AS
, R
AS
must
be less than the maximum value of 10 kΩ. The maximum value of 10 kΩ for R
AS
is to ensure low sampling
error in the worst case condition of maximum ΔV
SAMP
and minimum C
AS
.