Datasheet

Appendix A Electrical Characteristics
MC9S08GB60A Data Sheet, Rev. 2
278 Freescale Semiconductor
A.9.3 SPI Timing
Table A-12 and Figure A-16 through Figure A-19 describe the timing requirements for the SPI system.
Table A-12. SPI Timing
No. Function Symbol Min Max Unit
Operating frequency
Master
Slave
f
op
f
Bus
/2048
dc
f
Bus
/2
f
Bus
/4
Hz
1
SCK period
Master
Slave
t
SCK
2
4
2048
—
t
cyc
t
cyc
2
Enable lead time
Master
Slave
t
Lead
1/2
1
—
—
t
SCK
t
cyc
3
Enable lag time
Master
Slave
t
Lag
1/2
1
—
—
t
SCK
t
cyc
4
Clock (SCK) high or low time
Master
Slave
t
WSCK
t
cyc
– 30
t
cyc
– 30
1024 t
cyc
—
ns
ns
5
Data setup time (inputs)
Master
Slave
t
SU
15
15
—
—
ns
ns
6
Data hold time (inputs)
Master
Slave
t
HI
0
25
—
—
ns
ns
7
Slave access time
t
a
—1t
cyc
8
Slave MISO disable time
t
dis
—1t
cyc
9
Data valid (after SCK edge)
Master
Slave
t
v
—
—
25
25
ns
ns
10
Data hold time (outputs)
Master
Slave
t
HO
0
0
—
—
ns
ns
11
Rise time
Input
Output
t
RI
t
RO
—
—
t
cyc
– 25
25
ns
ns
12
Fall time
Input
Output
t
FI
t
FO
—
—
t
cyc
– 25
25
ns
ns