Datasheet

Chapter 2 Pins and Connections
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 31
For information about controlling these pins as general-purpose I/O pins, see Chapter 6, “Parallel
Input/Output.” For information about how and when on-chip peripheral systems use these pins, refer to the
appropriate section from Table 2-1.
When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. See Chapter 6, “Parallel Input/Output” for details.
Pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever the pin
is acting as an input even if it is being controlled by an on-chip peripheral module. When the PTA7–PTA4
pins are controlled by the KBI module and are configured for rising-edge/high-level sensitivity, the pullup
enable control bits enable pulldown devices rather than pullup devices. Similarly, when IRQ is configured
as the IRQ input and is set to detect rising edges, the pullup enable control bit enables a pulldown device
rather than a pullup device.
Table 2-1. Pin Sharing References
Port Pins
Alternate
Function
Reference
1
1
See this section for information about modules that share these pins.
PTA7–PTA0 KBI1P7–KBI1P0 Chapter 2, “Pins and Connections”
PTB7–PTB0 AD1P7–AD1P0 Chapter 14, “Analog-to-Digital Converter (S08ATDV3)”
PTC7–PTC4 — Chapter 6, “Parallel Input/Output”
PTC3–PTC2 SCL1–SDA1 Chapter 13, “Inter-Integrated Circuit (S08IICV1)”
PTC1–PTC0 RxD2–TxD2 Chapter 11, “Serial Communications Interface (S08SCIV1)”
PTD7–PTD3
TPM2CH4–
TPM2CH0
Chapter 10, “Timer/PWM (S08TPMV1)”
PTD2–PTD0
TPM1CH2–
TPM1CH0
Chapter 10, “Timer/PWM (S08TPMV1)”
PTE7–PTE6 — Chapter 6, “Parallel Input/Output”
PTE5
PTE4
PTE3
PTE2
SPSCK1
MISO1
MOSI1
SS1
Chapter 12, “Serial Peripheral Interface (S08SPIV3)”
PTE1–PTE0 RxD1–TxD1 Chapter 11, “Serial Communications Interface (S08SCIV1)”
PTF7–PTF0 — Chapter 6, “Parallel Input/Output”
PTG7–PTG3 — Chapter 6, “Parallel Input/Output”
PTG2–PTG1 EXTAL–XTAL Chapter 7, “Internal Clock Generator (S08ICGV2)”
PTG0 BKGD/MS Chapter 15, “Development Support”