Datasheet

Chapter 6 Parallel Input/Output
MC9S08GB60A Data Sheet, Rev. 2
Freescale Semiconductor 99
6.6.6 Port F Registers (PTFD, PTFPE, PTFSE, and PTFDD)
Port F includes eight general-purpose I/O pins that are not shared with any peripheral module. Port F pins
used as general-purpose I/O pins are controlled by the port F data (PTFD), data direction (PTFDD), pullup
enable (PTFPE), and slew rate control (PTFSE) registers.
76543210
R
PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0
W
Reset00000000
Figure 6-29. Port PTF Data Register (PTFD)
Table 6-21. PTFD Field Descriptions
Field Description
7:0
PTFD[7:0]
Port PTF Data Register Bits — For port F pins that are inputs, reads return the logic level on the pin. For port
F pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port F pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTFD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
76543210
R
PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0
W
Reset00000000
Figure 6-30. Pullup Enable for Port F (PTFPE)
Table 6-22. PTFPE Field Descriptions
Field Description
7:0
PTFPE[7:0]
Pullup Enable for Port F Bits — For port F pins that are inputs, these read/write control bits determine whether
internal pullup devices are enabled. For port F pins that are configured as outputs, these bits are ignored and the
internal pullup devices are disabled.
0 Internal pullup device disabled.
1 Internal pullup device enabled.