Datasheet

Resets, Interrupts, and System Configuration
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor 73
5.7.3 System Background Debug Force Reset Register (SBDFR)
This register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
3
ILAD
Illegal Address — Reset was caused by an attempt to access a designated illegal address.
0 Reset not caused by an illegal address access.
1 Reset caused by an illegal address access.
Illegal address areas in the MC9S08GT16A are:
• 0x0880 - 0x17FF — Gap from end of RAM to start of high page registers
• 0x182C - 0xBFFF — Gap from end of high page registers to start of Flash memory
Unused and reserved locations in register areas are not considered designated illegaladdresses and do not
triggerillegal address resets.
2
ICG
Internal Clock Generation Module Reset — Reset was caused by an ICG module reset.
0 Reset not caused by ICG module.
1 Reset caused by ICG module.
1
LVD
Low Voltage Detect — If the LVD reset is enabled (LVDE = LVDRE = 1) and the supply drops below the LVD trip
voltage, an LVD reset occurs. The LVD function is disabled when the MCU enters stop. To maintain LVD operation
in stop, the LVDSE bit must be set.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
76543210
R00000000
W BDFR
Note
(1)
1
BDFR is writable only through serial background debug commands, not from user programs.
Reset 00000000
= Unimplemented or Reserved
Table 5-4. SBDFR Field Descriptions
Field Description
0
BDFR
Background Debug Force Reset — A serial background mode command such as WRITE_BYTE allows an
external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be
written from a user program.
Table 5-3. SRS Field Descriptions (continued)
Field Description