Datasheet

Internal Clock Generator (S08ICGV4)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor 135
9.3.4 ICG Status Register 2 (ICGS2)
9.3.5 ICG Filter Registers (ICGFLTU, ICGFLTL)
76543210
R0000000DCOS
W
Reset 00000000
= Unimplemented or Reserved
Figure 9-9. ICG Status Register 2 (ICGS2)
Table 9-4. ICGS2 Register Field Descriptions
Field Description
0
DCOS
DCO Clock Stable — The DCOS bit is set when the DCO clock (ICG2DCLK) is stable, meaning the count error
has not changed by more than n
unlock
for two consecutive samples and the DCO clock is not static. This bit is
used when exiting off state if CLKS = X1 to determine when to switch to the requested clock mode. It is also used
in self-clocked mode to determine when to start monitoring the DCO clock. This bit is cleared upon entering the
off state.
0 DCO clock is unstable.
1 DCO clock is stable.
76543210
R0000
FLT
W
Reset 00000000
= Unimplemented or Reserved
Figure 9-10. ICG Upper Filter Register (ICGFLTU)
Table 9-5. ICGFLTU Register Field Descriptions
Field Description
3:0
FLT
Filter Value — The FLT bits indicate the current filter value, which controls the DCO frequency. The FLT bits are
read only except when the CLKS bits are programmed to self-clocked mode (CLKS = 00). In self-clocked mode,
any write to ICGFLTU updates the current 12-bit filter value. Writes to the ICGFLTU register will not affect FLT if
a previous latch sequence is not complete.