Datasheet

Analog-to-Digital Converter (S08ATDV3)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Freescale Semiconductor 227
Table 14-3. Available Result Data Formats
RES8 DJM SGN Data Formats of Result
Analog Input
V
REFH
=V
DDA
, V
REFL
=V
SSA
ATDRH:ATDRL
V
DDA
V
SSA
1 0 0 8-bit : left justified : unsigned $FF:$00 $00:$00
1 0 1 8-bit : left justified : signed $7F:$00 $80:$00
11
X
1
1
The SGN bit is only effective when DJM = 0. When DJM = 1, SGN is ignored.
8-bit : left justified
2
: unsigned
2
8-bit results are always in ATDRH.
$FF:$00 $00:$00
0 0 0 10-bit : left justified : unsigned $FF:$C0 $00:$00
0 0 1 10-bit : left justified : signed $7F:$C0 $80:$00
01
X
1
10-bit : right justified : unsigned $03:$FF $00:$00
Table 14-4. Clock Prescaler Values
PRS Factor = (PRS +1) × 2
Max Bus Clock
MHz
(2 MHz max ATD Clock)
1
1
Maximum ATD conversion clock frequency is 2 MHz. The max bus clock frequency is computed from the max ATD conversion
clock frequency times the indicated prescaler setting; i.e., for a PRS of 0, max bus clock = 2 (max ATD conversion clock
frequency) × 2 (Factor) = 4 MHz.
Max Bus Clock
MHz
(1 MHz max ATD Clock)
2
2
Use these settings if the maximum desired ATD conversion clock frequency is 1 MHz. The max bus clock frequency is
computed from the max ATD conversion clock frequency times the indicated prescaler setting; i.e., for a PRS of 0, max bus
clock = 1 (max ATD conversion clock frequency) × 2 (Factor) = 2 MHz.
Min Bus Clock
3
MHz
(500 kHz min ATD Clock)
3
Minimum ATD conversion clock frequency is 500 kHz. The min bus clock frequency is computed from the min ATD conversion
clock frequency times the indicated prescaler setting; i.e., for a PRS of 1, min bus clock = 0.5 (min ATD conversion clock
frequency) × 2 (Factor) = 1 MHz.
0000 2421
0001 4842
0010 6 12 6 3
0011 8 16 8 4
0100 10 20 10 5
0101 12 20 12 6
0110 14 20 14 7
0111 16 20 16 8
1000 18 20 18 9
1001 20 20 20 10
1010 22 20 20 11
1011 24 20 20 12
1100 26 20 20 13
1101 28 20 20 14
1110 30 20 20 15
1111 32 20 20 16