Datasheet

Analog-to-Digital Converter (S08ATDV3)
MC9S08GT16A/GT8A Data Sheet, Rev. 1
228 Freescale Semiconductor
14.3.2 ATD Status and Control (ATDSC)
Writes to the ATD status and control register clears the CCF flag, cancels any pending interrupts, and
initiates a new conversion.
76543210
R CCF
ATDIE ATDCO
ATDCH
W
Reset 00000001
= Unimplemented or Reserved
Figure 14-6. ATD Status and Control Register (ATDSC)
Table 14-5. ATDSC Register Field Descriptions
Field Description
7
CCF
Conversion Complete Flag — The CCF is a read-only bit which is set each time a conversion is complete. The
CCF bit is cleared whenever the ATDSC register is written. It is also cleared whenever the result registers,
ATDRH or ATDRL, are read.
0 Current conversion is not complete.
1 Current conversion is complete.
6
ATDIE
ATD Interrupt Enabled — When this bit is set, an interrupt is generated upon completion of an ATD conversion.
At this time, the result registers contain the result data generated by the conversion. The interrupt will remain
pending as long as the conversion complete flag CCF is set. If the ATDIE bit is cleared, then the CCF bit must
be polled to determine when the conversion is complete. Note that system reset clears pending interrupts.
0 ATD interrupt disabled.
1 ATD interrupt enabled.
5
ATDCO
ATD Continuous Conversion — When this bit is set, the ATD will convert samples continuously and update the
result registers at the end of each conversion. When this bit is cleared, only one conversion is completed between
writes to the ATDSC register.
0 Single conversion mode.
1 Continuous conversion mode.
4:0
ATDCH
Analog Input Channel Select — This field of bits selects the analog input channel whose signal is sampled and
converted to digital codes. Table 14-6 lists the coding used to select the various analog input channels.
Table 14-6. Analog Input Channel Select Coding
ATDCH Analog Input Channel
00 AD0
01 AD1
02 AD2
03 AD3
04 AD4
05 AD5
06 AD6
07 AD7
08–1D
Reserved (default to V
REFL
)
1E
V
REFH
1F
V
REFL