Datasheet

Parallel Input/Output
MC9S08GT16A/GT8A Data Sheet, Rev. 1
94 Freescale Semiconductor
76543210
R
000
PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0
W
Reset 00000000
Figure 6-22. Slew Rate Control Enable for Port D (PTDSE)
Table 6-15. PTDSE Field Descriptions
Field Description
4:0
PTDSE[4:0]
Slew Rate Control Enable for Port D Bits — For port D pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port D pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
76543210
R
000
PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0
W
Reset 00000000
Figure 6-23. Data Direction for Port D (PTDDD)
Table 6-16. PTDDD Field Descriptions
Field Description
4:0
PTDDD[4:0]
Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for
PTDD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn.