Datasheet

Chapter 1 Device Overview
MC9S08JM16 Series Data Sheet, Rev. 2
Freescale Semiconductor 21
Table 1-2 lists the functional versions of the on-chip modules.
1.3 System Clock Distribution
Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock
inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module
functions. All memory mapped registers associated with the modules are clocked with BUSCLK.
Figure 1-2. System Clock Distribution Diagram
Table 1-2. Versions of On-Chip Modules
Module Version
Analog Comparator (ACMP) 2
Analog-to-Digital Converter (ADC) 1
Central Processing Unit (CPU) 2
IIC Module (IIC) 2
Keyboard Interrupt (KBI) 2
Multi-Purpose Clock Generator (MCG) 1
Real-Time Counter (RTC) 1
Serial Communications Interface (SCI) 4
8-/16-bit Serial Peripheral Interface (SPI16) 1
Timer Pulse-Width Modulator (TPM) 3
Universal Serial Bus (USB) 1
Debug Module (DBG) 2
TPM1 TPM2
USB
MCG
MCGOUT
÷2
BUSCLK
MCGLCLK
MCGERCLK
COP
1. The FFCLK is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency.
2. ADC has min. and max. frequency requirements. See Chapter 10, “Analog-to-Digital Converter (S08ADC12V1),” and Appendix A, “Electrical
Characteristics,” for details.
3. Flash has frequency requirements for program and erase operation. See Appendix A, “Electrical Characteristics,” for details.
XOSC
EXTAL XTAL
FFCLK
1
MCGFFCLK
RTC
1 kHz
LPO
TPMCLK
MCGIRCLK
÷2
IIC
SCI1
SCI2
SPI1
SPI1
BDCCPUUSB
RAM
ADC
2
RAM FLASH
3
LPO clock