Datasheet

Chapter 5 Resets, Interrupts, and System Configuration
MC9S08JM16 Series Data Sheet, Rev. 2
Freescale Semiconductor 67
5.6 Low-Voltage Detect (LVD) System
The MC9S08JM16 series includes a system to protect memory contents against low voltage conditions and
control MCU system states during supply voltage variations. The system is composed of a power-on reset
(POR) circuit and an LVD circuit with a user selectable trip voltage, either high (V
LVD H
) or low (V
LVDL
).
The LVD circuit is enabled when LVDE in SPMSC1 is high and the trip voltage is selected by LVDV in
SPMSC2. The LVD is disabled upon entering any of the stop modes unless the LVDSE bit is set. If LVDSE
and LVDE are both set, then the MCU cannot enter stop2, and the current consumption in stop3 with the
LVD enabled will be greater.
5.6.1 Power-On Reset Operation
When power is initially applied to the MCU, or when the supply voltage drops below the V
POR
level, the
POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the chip in
reset until the supply has risen above the V
LVDL
level. Both the POR bit and the LVD bit in SRS are set
following a POR.
5.6.2 LVD Reset Operation
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. After an LVD reset has occurred, the LVD system will hold the MCU in reset until the supply
voltage has risen above the level determined by LVDV. The LVD bit in the SRS register is set following
an LVD reset or POR.
5 0xFFF4:FFF5 Vspi1 SPI1
SPRF
MODF
SPTEF
SPMF
S P I E
SP IE
SP TI E
SPMIE
SPI1
4 0xFFF6:FFF7 Vlol MCG LOLS LOLIE MCG loss of lock
3 0xFFF8:FFF9 Vlvd
System
control
LVDF LVDIE Low-voltage detect
2 0xFFFA:FFFB Virq IRQ IRQF IRQIE IRQ pin
1 0xFFFC:FFFD Vswi Core SWI Instruction — Software interrupt
0 0xFFFE:FFFF Vreset
System
control
COP
LVD
RESET
pin
Illegal opcode
Illegal address
LOC
POR
BDFR
C O P E
L V D R E
—
ILOP
ILAD
C ME
POR
Watchdog timer
Low-voltage detect
External pin
Illegal opcode
Illegal address
Loss of clock
Power-on-reset
BDM-forced reset
Table 5-1. Vector Summary (from Lowest to Highest Priority) (continued)
Vector
Number
Address
(High/Low)
Vector Name Module Source Enable Description