Datasheet

Chapter 6 Parallel Input/Output
MC9S08JM16 Series Data Sheet, Rev. 2
Freescale Semiconductor 81
6.5.2 Port A Pin Control Registers (PTAPE, PTASE, PTADS)
In addition to the I/O control, port A pins are controlled by the registers listed below.
76543210
R
PTAPE5 PTAPE0
W
Reset00000000
Figure 6-4. Internal Pullup Enable for Port A (PTAPE)
Table 6-3. PTADD Register Field Descriptions
Field Description
5,0
PTAPE[5,0]
Internal Pullup Enable for Port A Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port A bit n.
1 Internal pullup device enabled for port A bit n.
76543210
R
PTASE5 PTASE0
W
Reset00111111
Figure 6-5. Output Slew Rate Control Enable for Port A (PTASE)
Table 6-4. PTASE Register Field Descriptions
Field Description
5,0
PTASE[5,0]
Output Slew Rate Control Enable for Port A Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
76543210
R
PTADS5 PTADS0
W
Reset00000000
Figure 6-6. Output Drive Strength Selection for Port A (PTASE)