Datasheet

Chapter 5 Resets, Interrupts, and System Configuration
MC9S08JM16 Series Data Sheet, Rev. 2
72 Freescale Semiconductor
5.7.5 System Options Register 2 (SOPT2)
Table 5-6. COP Configuration Options
Control Bits
Clock Source
COP Window
1
Opens
(COPW = 1)
1
Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column
displays the minimum number of clock counts required before the COP timer can be reset in windowed COP mode (COPW = 1).
COP Overflow Count
COPCLKS COPT[1:0]
N/A 0:0 N/A N/A COP is disabled
0 0:1 1 kHz LPO
clock
N/A
2
5
cycles (32 ms
2
)
2
Values shown in milliseconds based on t
LPO
= 1 ms. See t
LPO
in the appendix Section A.12.1, “Control Timing,” for the
tolerance of this value.
0 1:0 1 kHz LPO
clock
N/A
2
8
cycles (256 ms
1
)
0 1:1 1 kHz LPO
clock
N/A
2
10
cycles (1.024 s
1
)
10:1
BUSCLK 6144 cycles
2
13
cycles
11:0
BUSCLK 49,152 cycles
2
16
cycles
11:1
BUSCLK 196,608 cycles
2
18
cycles
76543210
R
COPCLKS
1
COPW
1
000
SPI1FE SPI2FE ACIC
W
Reset00000110
= Unimplemented or Reserved
1
This bit can be written only one time after reset. Additional writes are ignored.
Figure 5-6. System Options Register 2 (SOPT2)
Table 5-7. SOPT2 Register Field Descriptions
Field Description
7
COPCLKS
COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.
0 Internal 1 KHz LPO clock is source to COP.
1 Bus clock is source to COP.
6
COPW
COP Window — This write-once bit selects the COP operation mode. When set, the 0x55-0xAA write sequence
to the SRS register must occur in the last 25% of the selected period. Any write to the SRS register during the
first 75% of the selected period will reset the MCU.
0 Normal COP operation.
1 Window COP operation.
2
SPI1FE
SPI1 Ports Input Filter Enable
0 Disable input filter on SPI1 port pins to allow for higher maximum SPI baud rate.
1 Enable input filter on SPI1 port pins to eliminate noise and restrict maximum SPI baud rate.