Datasheet

MC9S08JS16 Series MCU Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor18
3.8 MCG Specifications
Table 9. MCG Frequency Specifications (Temperature Range = –40 to 85°C Ambient)
Num C Rating Symbol Min Typical Max Unit
1 C Average internal reference frequency — untrimmed
f
int_ut
25 32.7 41.66 kHz
2 P Average internal reference frequency — trimmed
f
int_t
31.25 — 39.0625 kHz
3 T Internal reference startup time
t
irefst
—60100μs
4 C DCO output frequency range — untrimmed
f
dco_ut
25.6 33.48 42.66 MHz
5 P DCO output frequency range — trimmed
f
dco_t
32 — 40 MHz
6C
Resolution of trimmed DCO output frequency at
fixed voltage and temperature (using FTRIM)
Δf
dco_res_t
— ±0.1 ±0.2
%f
dco
7C
Resolution of trimmed DCO output frequency at
fixed voltage and temperature (not using FTRIM)
Δf
dco_res_t
— ±0.2 ±0.4
%f
dco
8P
Total deviation of trimmed DCO output frequency
over voltage and temperature
Δf
dco_t
—
0.5
–1.0
±2
%f
dco
9C
Total deviation of trimmed DCO output frequency
over fixed voltage and temperature range of
0–70 °C
Δf
dco_t
— ±0.5 ±1
%f
dco
10 C
FLL acquisition time
1
1
This specification applies any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
t
fll_acquire
—— 1ms
11 D
PLL acquisition time
2
2
This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it
is already running.
t
pll_acquire
—— 1ms
12 C
Long term Jitter of DCO output clock (averaged over
2ms interval)
3
C
Jitter
—0.020.2
%f
dco
13 D VCO operating frequency
f
vco
7.0 — 55.0 MHz
14 D PLL reference frequency range
f
pll_ref
1.0 — 2.0 MHz
15 T
Long term accuracy of PLL output clock (averaged
over 2 ms)
f
pll_jitter_2ms
—
0.590
4
—%
16 T
Jitter of PLL output clock measured over 625 ns
5
f
pll_jitter_625ns
—
0.566
4
—%
17 D
Lock entry frequency tolerance
6
D
lock
±1.49 — ±2.98 %
18 D
Lock exit frequency tolerance
7
D
unl
±4.47 — ±5.97 %
19 D Lock time — FLL
t
fll_lock
——
t
fll_acquire+
1075(1/
f
int_t)
s
20 D Lock time — PLL
t
pll_lock
——
t
pll_acquire+
1075(1/
f
pll_ref)
s
21 D
Loss of external clock minimum frequency —
RANGE = 0
f
loc_low
(3/5) x f
int
— — kHz
22 D
Loss of external clock minimum frequency —
RANGE = 1
f
loc_high
(16/5) x f
int
— — kHz