Datasheet

Chapter 9 Liquid Crystal Display Driver (S08LCDV1)
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
130 Freescale Semiconductor
9.3.3 LCD Frontplane Enable Registers 0–5 (FPENR0–FPENR5)
When LCDEN = 1, these bits enable the frontplane output waveform on the corresponding frontplane pin.
Read: anytime
Write: anytime
76543210
FPENR0
R
FP7EN FP6EN FP5EN FP4EN FP3EN FP2EN FP1EN FP0EN
W
Reset 0 0 0 0 0 0 0 0
FPENR1
R
FP15EN FP14EN FP13EN FP12EN FP11EN FP10EN FP9EN FP8EN
W
Reset 0 0 0 0 0 0 0 0
FPENR2
R
FP23EN FP22EN FP21EN FP20EN FP19EN FP18EN FP17EN FP16EN
W
Reset 0 0 0 0 0 0 0 0
FPENR3
R
FP31EN FP30EN FP29EN FP28EN FP27EN FP26EN FP25EN FP24EN
W
Reset 0 0 0 0 0 0 0 0
FPENR4
R
FP39EN FP38EN FP37EN FP36EN FP35EN FP34EN FP33EN FP32EN
W
Reset 0 0 0 0 0 0 0 0
FPENR5
R
0 0 0 0 0 0 0
FP40EN
W
Reset 0 0 0 0 0 0 0 0
Unimplemented or Reserved
Table 9-6. FPENR0–FPENR5 Field Descriptions
Field Description
40:0
FP[40:0]EN
Frontplane Output Enable — The FP[40:0]EN bit enables the frontplane driver outputs. If LCDEN = 0, these
bits have no effect on the state of the I/O pins.It is recommended to set FP[40:0]EN bits before LCDEN is set.
0 Frontplane driver output disabled on FPnn.
1 Frontplane driver output enabled on FPnn.