Datasheet

Chapter 9 Liquid Crystal Display Driver (S08LCDV1)

MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4

Freescale Semiconductor 133

9.3.4.1 LCDRAM Registers as On/Off Selector (LCDDRMS = 0)

If LCDDRMS bit in the LCDCMD register is deasserted, the LCDRAM register accesses a register bank

that controls the on/off state for frontplane drivers.

9.3.4.2 LCDRAM Registers as Blink Enable/Disable (LCDDRMS = 1)

If LCDDRMS in the LCDCMD register is asserted, the LCDRAM register accesses a register bank that

controls the blink enables/disables for each individual LCD segment

9.3.5 LCD Clock Source Register (LCDCLKS)

Read: anytime

Write: anytime.It is recommended that CLKADJ[5:0], DIV16, and SOURCE not be modiﬁed while the

LCDEN bit is asserted.

Table 9-7. LCDRAM Field Descriptions (when LCDDRMS = 0)

Field Description

FP[n]BP[x] Segment On — If LCDDRMS in the LCDCMD is deasserted (LCDDRMS=0), the FP[n]BP[x] bit in the LCDRAM

registers controls on/off state for the LCD segment connected between FP[n] and BP[x].Asserting the FP[n]BP[x]

bit displays (turns on) the LCD segment connected between FP[n] and BP[x].

0 LCD segment off.

1 LCD segment on.

Table 9-8. LCDRAM Field Descriptions (when LCCDRMS = 1)

Field Description

FP[n]BP[x] LCD Segment Blink Enable — If LCDDRMS bit in the LCDCMD is asserted (LCDDRMS=1), the FP[n]BP[x] bit

in the LCDRAM registers controls blink mode enable/disable state for the LCD segment connected between

FP[n] and BP[x].Asserting the FP[n]BP[x] bit enable the blink mode for the LCD segment connected between

FP[n] and BP[x] if the associated bit when LCDDRMS = 0 is also set.

0 Disables blink enable for LCD segment.

1 Enables blink enable for LCD segment.

76543210

SOURCE DIV16 CLKADJ5 CLKADJ4 CLKADJ3 CLKADJ2 CLKADJ1 CLKADJ0

Reset 00000101

Figure 9-6. LCD Clock Source Register (LCDCLKS)