Datasheet

Chapter 9 Liquid Crystal Display Driver (S08LCDV1)
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Freescale Semiconductor 135
9.3.7 LCD Blink Control Register (LCDBCTL)
Read: anytime
Write: anytime. It is recommended that BRATE[1:0] and BLKMODE, must not be modified while BLINK
is asserted.
5:4
CPCADJ[1:0]
LCD Module Charge Pump Clock Adjust- Adjust the clock source for the charge pump
Charge Pump Clock Rate
= LCDCLK / (6 × 2
(C
PADJ[1:0] +1)
) Eqn. 9-3
00 Configures for 2728 Hz charge pump frequency (LCDCLK = 32.768khz)
01 Configures for 1364 Hz charge pump frequency (LCDCLK = 32.768khz)
10 Configures for 682 Hz charge pump frequency (LCDCLK = 32.768khz)
11 Configures for 341 Hz charge pump frequency (LCDCLK = 32.768khz)
3
HDRVBUF
High Drive Buffer Mode Select — This bit enhances the VLCD buffer drive active high buffer drive for larger
capacitance LCD glass. (See Figure 9-17 for details.)
0 Normal buffer drive. (Ideal for 2000 pF LCD glass.)
1 High buffer drive. (Ideal for 4000 pF LCD glass.)
2
BBYPASS
Op Amp Control— Determines whether the internal LCD op amp buffer is bypassed. (See Figure 9-17 for
details)
0 Buffered mode
1 Unbuffered mode
1:0
VSUPPLY[1:0]
Voltage Supply Control— Configures whether the LCD module power supply is external or internal. It is
recommended that this bit field not be modified while the LCD module is enabled (e.g., LCDEN = 1). See
Figure 9-17 for more detail.
76543210
R
BLINK
0 0 0
BLKMODE BRATE2 BRATE1 BRATE0
W
Reset 00000000
Unimplemented or Reserved
Figure 9-8. LCD Blink Control Register (LCDBCTL)
Table 9-10. LCDSUPPLY Field Descriptions (continued)
Field Description