Datasheet

Chapter 9 Liquid Crystal Display Driver (S08LCDV1)
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
158 Freescale Semiconductor
9.5.2.1 Initialization Example 1
Example 1 LCD setup requirements are reiterated in the following table:
Table 9-22 lists the required setup values required to initialize the LCD as specified by Example 1:
Example
Operating
Voltage,
V
DD
LCD Clock
Source
LCD Glass
Operating
Voltage
Required
LCD
segments
LCD
Frame
Rate
Blinking
Mode/Rate
Behavior in
STOP3 and
WAIT modes
LCD Power
Input
1 1.8-V External
32.768 kHz
3-V 128 30 Hz No Blinking WAIT: on
STOP3: on
Power via
V
LCD
Table 9-22. Initialization Register Values for Example 1
Register
bit or
bit field
Binary
Value
Comment
LCDCLKS
00000000
SOURCE 0 Selects the external clock reference as the LCD clock input
External clock reference = 0; Bus clock = 1
DIV16 0 Adjusts the LCD clock input (see table 9-12)
CLKADJ[5:0] 000000 Adjusts the LCD clock input (see table 9-12)
LCDSUPPLY
10XXXX10
LCDCPEN 1 Enable the charge pump
LCDCPMS 0 For 3-V LCD glass, select doubler mode; Doubler mode = 0; Tripler mode = 1
HDRVBUF X High drive buffer
CPCADJ[1:0] XX Configure LCD charge pump clock source
BBYPASS X Buffer Bypass; Buffer mode = 0; Unbuffered mode = 1
VSUPPLY[1:0] 10 When VSUPPLY[1:0] = 10, the LCD must be externally powered via V
LCD
(see
table 9-16). For 3-V glass, the nominal value of V
LCD
should be 1.5-V.
LCDCR1
XXXXXX00
LCDIEN X LCD Interrupt Enable
LCDWAI 0 LCD is “on” in WAIT mode
LCDSTP3 0 LCD is “on” in STOP3 mode
LCDCR0
0X100X00
LCLK[2:0] 100 For 1/4 duty cycle, select closest value to the desired 30 Hz LCD frame frequency
(see table 9-13)
LPWAVE X Low power waveform
DUTY[1:0] 11 For 128 segments (4x32), select 1/4 duty cycle (see table 9-11)
LCDBCTL
0XXXXXXX
BLKMODE X N/A; Blink Segments = 0; Blink All = 1
BRATE[2:0] XXX N/A
FPENR[5:0] FPENR0
FPENR1
FPENR2
FPENR3
FPENR4
FPENR5
11111111
11111111
11111111
11111111
00000000
XXXXXXX0
Only 32 Frontplanes need to be enabled.