Datasheet

Chapter 9 Liquid Crystal Display Driver (S08LCDV1)
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Freescale Semiconductor 159
9.5.2.2 Initialization Example 2
Example 2 LCD setup requirements are reiterated in the following table:
Table 9-23 lists the required setup values required to initialize the LCD as specified by Example 2:
Example
Operating
Voltage,
V
DD
LCD Clock
Source
LCD Glass
Operating
Voltage
Required
LCD
segments
LCD
Frame
Rate
Blinking
Mode/Rate
Behavior in
STOP3 and
WAIT modes
LCD Power
Input
2 3.6-V Internal
100 kHz
3-V 99 80 Hz Individual segment
0.5 Hz
WAIT: on
STOP3: off
Power via
V
DD
Table 9-23. Initialization Register Values for Example 2
Register Bit/bit field
Binary
Value
Comment
LCDCLKS
10000010
SOURCE 1 Selects the bus clock as the LCD clock input
External clock reference = 0; Bus clock = 1
DIV16 0 Adjusts the LCD clock input (see table 9-12)
CLKADJ[5:0] 000010 Adjusts the LCD clock input (see table 9-12)
LCDSUPPLY
1XXXXX01
LCDCPEN 1 Enable the charge pump
LCDCPMS X Don’t care since power is from internal V
DD
Doubler mode = 0; Tripler mode = 1
HDRVBUF X High drive buffer
CPCADJ[1:0] XX Configure LCD charge pump clock source
BBYPASS X Buffer Bypass; Buffer mode = 0; Unbuffered mode = 1
VSUPPLY[1:0] 01 Power LCD via V
DD
internal power (see table 9-16). When VSUPPLY[1:0] = 01,
V
LL3
is generated from V
DD .
LCDCR1
XXXXXX01
LCDWAI 0 LCD is “on” in WAIT mode
LCDSTP3 1 LCD is “off” in STOP3 mode
LCDCR0
0X011X11
LCLK[2:0] 011 For 1/3 duty cycle, select closest value to the desired 80 Hz LCD frame frequency
(see table 9-13). Note the LCD base frequency - 256.2 Hz
LPWAVE X Low power waveform
DUTY[1:0] 10 For 99 segments (3x33), select 1/3 duty cycle (see table 9-11)