Datasheet

Chapter 9 Liquid Crystal Display Driver (S08LCDV1)
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Freescale Semiconductor 163
9.6 Application Information
Figure 9-18 is a programmer’s model of the LCD module. The programmer’s model groups the LCD
module register bit and bit field into functional groups. The model is a very high level illustration of the
LCD module showing the module’s functional hierarchy including initialization and runtime control.
Figure 9-18. LCD Programmer’s Model Diagram
9.6.1 LCD Seven Segment Example Description
A description of the connection between the LCD module and a seven segment LCD character is illustrated
below to provide a basic example for a LPWAVE = 0 and 1/3 duty cycle LCD implementation. The
example use backplane pins (BP0, BP1, BP2) and frontplace pins (FP0, FP1, and FP2). LCDRAM
contents and output waveforms are also shown. Output waveforms are illustrated in Figure 9-19 and
Figure 9-20.
Frame Frequency
DUTY[1:0]
LCLK[2:0]
FP[40:0]
BP[3:0]
Blink Enable
BLKMODE
LCDBCTL
LCDDRMS = 1
BLINK
Power Options
LCDCPMS
LCDCPEN
VSUPPLY[1:0]
BBYPASS
Low Power
LCDWAI
LCDSTP3
LCD Frame
LCDIEN
LCDIF
Initialization Options
FPENR[5:0]
LCD Segment Energize
LCDDRMS = 0
Data Bus
LCD Segment Display and Blink Control
LCDCLR
BLANK
LCDRAM
LCD Power Pins
V
cap1
V
cap2
C
BYLCD
V
LCD
V
LL3
V
LL2
V
LL1
X
LCD charge pump capacitance
NOTE: Configured
for power using
internal V
DD
LCD GLASS PANEL
LCD Pin Enable
LCDEN
Blink Rate
SOURCE
DIV16
CLKADJ[5:0]
Internal Clock Generator
External Crystal = 32.768 kHz
Input Clock Source
Shown with 7-segment
LCD glass hardware
(not all LCD pins used)
Frequency
LCDCR0
BRATE[2:0]
LCDCLKS
LCDCR1
LCDMISC
LCDCR1
LCDCR0
Module Enable
BLKMODE
LCDBCTL
LCDRAM
LCDBCTL
LCDMISC
LCDCR1
LCDMISC
Interrupt
Segment Blink
Segment Energize
Enable
Blink LCDRAM
LCDRAM Mode Select
and Command
Mode Select
FP[40:0]EN
FP[40:0]BP[3:0]
FP[40:0]BP[3:0]
Clear Display
C
LCD
HDRVBUF