Datasheet

Chapter 10 Internal Clock Generator (S08ICGV4)
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Freescale Semiconductor 169
Chapter 10
Internal Clock Generator (S08ICGV4)
10.1 Introduction
The ICG module is used to generate the system clocks for the MC9S08LC60/36/20 MCU. Figure 10-1
shows the clock distribution for the MC9S08LC60/36/20 MCU. Electrical parametric data for the ICG
may be found in Appendix.
Figure 10-1. System Clock Distribution Diagram
NOTE
Freescale Semiconductor programs a factory trim value for ICGTRM into
the FLASH location $FFBE (NVICGTRM). Leaving this address for the
ICGTRM value also allows debugger and programmer vendors to perform
a manual trim operation and store the resultant ICGTRM value into
NVICGTRM for users to access at a later time. The value in NVICGTRM
is not automatically loaded and therefore must be copied into ICGTRM by
user code.
Figure 10-2 shows the MC9S08LC60 Series block diagram with the ICG highlighted.
TPMCLK
ADC has min and max
frequency requirements.
See Chapter 1, “Introduction”
and the Electricals Appendix.
FLASH has frequency
requirements for program
and erase operation.
See the Electricals Appendix.
* ICGLCLK is the alternate BDC clock source for the MC9S08LC60 Series.
TPM1 TPM2 IIC1
SCI SPI1 SPI2
BDCCPU
ICG
ICGOUT
÷2
FFE
SYSTEM
LOGIC
BUSCLK
ICGLCLK*
CONTROL
FIXED FREQ CLOCK
ICGERCLK
÷2
ADC
RAM FLASH
LCD
ACMP
COP
1-kHz
(XCLK)
RTI