Datasheet

Chapter 12 Serial Communications Interface (S08SCIV3)
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Freescale Semiconductor 219
12.2 Register Definition
The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for
transmit/receive data.
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all SCI registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
12.2.1 SCI Baud Rate Registers (SCIBDH, SCIBHL)
This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud
rate setting [SBR12:SBR0], first write to SCIBDH to buffer the high half of the new value and then write
to SCIBDL. The working value in SCIBDH does not change until SCIBDL is written.
SCIBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first
time the receiver or transmitter is enabled (RE or TE bits in SCIC2 are written to 1).
76543210
R000
SBR12 SBR11 SBR10 SBR9 SBR8
W
Reset 00000000
= Unimplemented or Reserved
Figure 12-5. SCI Baud Rate Register (SCIBDH)
Table 12-1. SCIBDH Register Field Descriptions
Field Description
4:0
SBR[12:8]
Baud Rate Modulo Divisor — These 13 bits are referred to collectively as BR, and they set the modulo divide
rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply
current. When BR = 1 to 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits in Table 12-2.
76543210
R
SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0
W
Reset 00000100
Figure 12-6. SCI Baud Rate Register (SCIBDL)