Datasheet

Chapter 15 Analog-to-Digital Converter (S08ADC12V1)
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
276 Freescale Semiconductor
15.3.5 Compare Value High Register (ADCCVH)
In 12-bit mode, the ADCCVH register holds the upper four bits of the 12-bit compare value. These bits are
compared to the upper four bits of the result following a conversion in 12-bit mode when the compare
function is enabled.
In 10-bit mode, the ADCCVH register holds the upper two bits of the 10-bit compare value (ADCV9 –
ADCV8). These bits are compared to the upper two bits of the result following a conversion in 10-bit mode
when the compare function is enabled.
In 8-bit mode, ADCCVH is not used during compare.
15.3.6 Compare Value Low Register (ADCCVL)
This register holds the lower 8 bits of the 12-bit or 10-bit compare value, or all 8 bits of the 8-bit compare
value. Bits ADCV7:ADCV0 are compared to the lower 8 bits of the result following a conversion in 12-bit,
10-bit or 8-bit mode.
15.3.7 Configuration Register (ADCCFG)
ADCCFG is used to select the mode of operation, clock source, clock divide, and configure for low power
or long sample time.
7654 3 210
R ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
W
Reset: 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 15-7. Data Result Low Register (ADCRL)
7654 3 210
R0000
ADCV11 ADCV10 ADCV9 ADCV8
W
Reset: 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 15-8. Compare Value High Register (ADCCVH)
7654 3 210
R
ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0
W
Reset: 0 0 0 0 0 0 0 0
Figure 15-9. Compare Value Low Register(ADCCVL)