Datasheet

Chapter 5 Resets, Interrupts, and System Configuration
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
64 Freescale Semiconductor
• Illegal opcode detect
• Background debug forced reset
• External pin reset (PIN) — can be disabled using RSTPE in SOPT2
• Clock generator loss of lock and loss of clock reset
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register. Whenever the MCU enters reset, the internal clock generator (ICG) module
switches to self-clocked mode with the frequency of f
Self_reset
selected. The reset pin is driven low for 34
internal bus cycles where the internal bus frequency is half the ICG frequency. After the 34 cycles are
completed, the pin is released and will be pulled up by the internal pullup resistor, unless it is held low
externally. After the pin is released, it is sampled after another 38 cycles to determine whether the reset pin
is the cause of the MCU reset.
5.4 Computer Operating Properly (COP) Watchdog
The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP timer periodically. If the application program gets lost and fails to reset the COP before it
times out, a system reset is generated to force the system back to a known starting point.
After any reset, the COPE becomes set in SOPT1 enabling the COP watchdog (see Section 5.8.4, “System
Options Register (SOPT1),” for additional information). If the COP watchdog is not used in an application,
it can be disabled by clearing COPE. The COP counter is reset by writing any value to the address of SRS.
This write does not affect the data in the read-only SRS. Instead, the act of writing to this address is
decoded and sends a reset signal to the COP counter.
The COPCLKS bit in SOPT2 (see Section 5.8.5, “System Options Register (SOPT2),” for additional
information) selects the clock source used for the COP timer. The clock source options are either the bus
clock or an internal 1kHz clock source. With each clock source, there is an associated short and long
time-out controlled by COPT in SOPT1. Table 5-1 summaries the control functions of the COPCLKS and
COPT bits. The COP watchdog defaults to operation from the 1kHz clock source and the associated long
time-out (2
8
cycles).
Table 5-1. COP Configuration Options
Control Bits
Clock Source COP Overflow Count
COPCLKS COPT
00
~1 kHz
2
5
cycles (32 ms)
1
1
Values are shown in this column based on t
RTI
= 1 ms. See t
RTI
in the appendix
Section A.10.1, “Control Timing,” for the tolerance of this value.
01
~1 kHz 2
8
cycles (256 ms)
1
10
Bus
2
13
cycles
11
Bus
2
18
cycles