Datasheet

Chapter 5 Resets, Interrupts, and System Configuration
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Freescale Semiconductor 73
5.8.3 System Background Debug Force Reset Register (SBDFR)
This register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x0000.
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
5.8.4 System Options Register (SOPT1)
This register may be read at any time. Bits 3 and 2 are unimplemented and always read 0. This is a
write-once register so only the first write after reset is honored. Any subsequent attempt to write to SOPT1
(intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. SOPT1
should be written during the user’s reset initialization program to set the desired controls even if the desired
settings are the same as the reset settings.
76543210
R00000000
W BDFR
1
1
BDFR is writable only through serial background debug commands, not from user programs.
Reset 00000000
= Unimplemented or Reserved
Table 5-5. SBDFR Field Descriptions
Field Description
0
BDFR
Background Debug Force Reset — A serial background mode command such as WRITE_BYTE allows an
external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be
written from a user program.
76543210
R
COPE COPT STOPE
00
BKGDPE RSTPE
W
Reset 11010011
= Unimplemented or Reserved
Figure 5-5. System Options Register (SOPT1)