Datasheet

Chapter 5 Resets, Interrupts, and System Configuration
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
74 Freescale Semiconductor
5.8.5 System Options Register (SOPT2)
This register may be read at any time.
Table 5-6. SOPT1 Field Descriptions
Field Description
7
COPE
COP Watchdog Enable — This write-once bit defaults to 1 after reset.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
6
COPT
COP Watchdog Timeout — This write-once bit selects the timeout period of the COP. COPT along with
COPCLKS in SOPT2 defines the COP timeout period.
0 Short timeout period selected.
1 Long timeout period selected.
5
STOPE
Stop Mode Enable — This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is
disabled and a user program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
1
BKGDPE
Background Debug Mode Pin Enable — The BKGDPE bit enables the PTG0/BKGD/MS pin to function as
BKGD/MS. When the bit is clear, the pin will function as PTG0, which is an output-only general-purpose I/O. This
pin always defaults to BKGD/MS function after any reset.
0 BKGD pin disabled.
1 BKGD pin enabled.
0
RSTPE
Reset Pin Enable — This write-once bit when set enables the PTB2/
RESET/ pin to function as
RESET. When clear, the pin functions as one of its input only alternative functions. This pin defaults to its
input-only port function following an MCU POR. Once configured for RESET pin, only POR can disable the
RESET pin function. When RSTPE is set, an internal pullup device is enabled on RESET.
0 PTB2/
RESET/ pin functions as PTB2.
1 PTB2/
RESET/ pin functions as RESET.
76543210
R
COPCLKS
1
1
This bit can be written only one time after reset. Additional writes are ignored.
000000
ACIC
W
Reset 00000000
= Unimplemented or Reserved
Figure 5-6. System Options Register (SOPT2)
Table 5-7. SOPT2 Field Descriptions
Field Description
7
COPCLKS
COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.
0 Internal 1-kHz clock is source to COP.
1 Bus clock is source to COP.
0
ACIC
Analog Comparator to Input Capture Enable— This bit connects the output of ACMP to TPM1 input channel 0.
0 ACMP output not connected to TPM1 input channel 0
1 ACMP output connected to TPM1 input channel 0.