Datasheet

Chapter 5 Resets, Interrupts, and System Configuration
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
78 Freescale Semiconductor
5.8.9 System Power Management Status and Control 2 Register (SPMSC2)
This register is used to configure the stop mode behavior of the MCU. For more information concerning
partial power down mode, see Section 3.6, “Stop Modes.”
1 This bit can be written only one time after reset. Additional writes are ignored.
Figure 5-11. System Power Management Status and Control 2 Register (SPMSC2)
76543210
R
0 0 0 PDF
PPDF
0
PDC
1
PPDC
1
W PPDACK
Reset 00000000
= Unimplemented or Reserved
Table 5-13. SPMSC2 Field Descriptions
Field Description
4
PDF
Power Down Flag — This read-only status bit indicates the MCU has recovered from stop1 mode.
0 MCU has not recovered from stop1 mode.
1 MCU recovered from stop1 mode.
3
PPDF
Partial Power Down Flag — The PPDF bit indicates that the MCU has exited the stop2 mode.
0 Not stop2 mode recovery.
1 Stop2 mode recovery.
2
PPDACK
Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit.
1
PDC
Power Down Control — The write-once PDC bit controls entry into the power down (stop2 and stop1) modes.
0 Power down modes are disabled.
1 Power down modes are enabled.
0
PPDC
Partial Power Down Control — The write-once PPDC bit controls which power down mode, stop1 or stop2, is
selected.
0 Stop1, full power down, mode enabled if PDC set.
1 Stop2, partial power down, mode enabled if PDC set.