Datasheet

Chapter 5 Resets, Interrupts, and System Configuration
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Freescale Semiconductor 79
5.8.10 System Power Management Status and Control 3 Register (SPMSC3)
This register is used to report the status of the low voltage warning function behavior of the MCU.
Figure 5-12. System Power Management Status and Control 3 Register (SPMSC3)
76543210
R
LVWF
0
LVDV LVWV
0000
W
LVWACK
Power-on reset
(POR):
0
(1)
1
LVWF will be set in the case when V
Supply
transitions below the trip point or after reset and V
Supply
is already below V
LVW
.
0000000
LVD reset
(LVR):
0
(1)
0uu0000
Any other
reset:
0
(1)
0uu0000
= Unimplemented or Reserved u = Unaffected by reset
Table 5-14. SPMSC3 Field Descriptions
Field Description
7
LVWF
Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status.
0 Low voltage warning not present.
1 Low voltage warning is present or was present.
6
LVWACK
Low-Voltage Warning Acknowledge — The LVWACK bit is the low-voltage warning acknowledge. Writing a 1
to LVWACK clears LVWF to 0 if a low voltage warning is not present.
5
LVDV
Low-Voltage Detect Voltage Select — The LVDV bit selects the LVD trip point voltage (V
LVD
).
0 Low trip point selected (V
LVD
= V
LVDL
).
1 High trip point selected (V
LVD
= V
LVDH
).
4
LVWV
Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (V
LVW
).
0 Low trip point selected (V
LVW
= V
LVWL
).
1 High trip point selected (V
LVW
= V
LVWH
).