Datasheet
Chapter 6 Parallel Input/Output
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
86 Freescale Semiconductor
6.2.2.2 Output Slew Rate Control Enable (PTASE)
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTASEn). When enabled, slew control limits the rate at which an output can transition in order to
reduce EMC emissions. Slew rate control has no effect on pins which are configured as inputs.
6.2.2.3 Output Drive Strength Select (PTADS)
An output pin can be selected to have high output drive strength by setting the corresponding bit in the
drive strength select register (PTADSn). When high drive is selected a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the chip are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin
to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this the EMC emissions may be affected by enabling pins as high drive.
76543210
R
PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
W
Reset 11111111
Figure 6-8. Slew Rate Control Enable for Port A (PTASE)
Table 6-4. PTASE Field Descriptions
Field Description
7:0
PTASE[7:0]
Slew Rate Control Enable for Port A Bits — For port A pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port A pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
76543210
R
PTADS7 PTADS6 PTADS5 PTADS4 PTADS3 PTADS2 PTADS1 PTADS0
W
Reset 00000000
Figure 6-9. Drive Strength Selection for Port A (PTADS)
Table 6-5. PTADS Field Descriptions
Field Description
7:0
PTADS[7:0]
Output Drive Strength Selection for Port A Bits—Each of these control bits selects between low and high output
drive for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port A bit n.
1 High output drive strength selected for port A bit n.