Datasheet

Chapter 6 Parallel Input/Output
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
90 Freescale Semiconductor
6.2.4.3 Output Drive Strength Select (PTBDS)
An output pin can be selected to have high output drive strength by setting the corresponding bit in the
drive strength select register (PTBDSn). When high drive is selected a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the chip are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin
to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this the EMC emissions may be affected by enabling pins as high drive.
6.2.5 Port C Registers
This section provides information about all registers and control bits associated with the parallel I/O ports.
The parallel I/O registers are located in page zero of the memory map.
Refer to tables in Chapter 4, “Memory” for the absolute address assignments for all parallel I/O registers.
This section refers to registers and control bits only by their names. A Freescale-provided equate or header
file normally is used to translate these names into the appropriate absolute addresses.
76543210
R
PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0
W
Reset 00000000
Figure 6-17. Drive Strength Selection for Port B (PTBDS)
Table 6-10. PTBDS Field Descriptions
Field Description
7:0
PTBDS[7:0]
Output Drive Strength Selection for Port B Bits—Each of these control bits selects between low and high output
drive for the associated PTB pin. For port B pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port B bit n.
1 High output drive strength selected for port B bit n.