Datasheet

Electrical Characteristics
MC9S08LG32 Series Data Sheet, Rev. 9
Freescale Semiconductor 29
2.11 AC Characteristics
This section describes timing characteristics for each peripheral system.
2.11.1 Control Timing
Figure 19. Reset Timing
Table 14. Control Timing
Num C Rating Symbol Min Typ
1
1
Typical values are based on characterization data at V
DD
= 5.0 V, 25 C unless otherwise stated.
Max Unit
1 D Bus frequency (t
cyc
= 1/f
Bus
)f
Bus
dc — 20 MHz
2 D Internal low power oscillator period t
LPO
700 — 1300 s
3 D External reset pulse width
2
2
This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
t
extrst
100 — — ns
4 D Reset low drive t
rstdrv
66 x t
cyc
——ns
5 D BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
t
MSSU
500 — — ns
6 D BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes
3
3
To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH
after V
DD
rises above V
LVD
.
t
MSH
100 — — s
7 D IRQ pulse width
Asynchronous path
2
Synchronous path
4
4
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
t
ILIH
t
IHIL
100
1.5 x t
cyc
—
—
—
—
ns
8 D Keyboard interrupt pulse width
Asynchronous path
2
Synchronous path
4
t
ILIH
t
IHIL
100
1.5 x t
cyc
—
—
—
—
ns
9 C Port rise and fall time — (load = 50 pF)
5, 6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
5
Timing is shown with respect to 20% V
DD
and 80% V
DD
levels. Temperature range –40 C to 105C.
6
Except for LCD pins in Open Drain mode.
t
Rise
t
Fall
—
—
3
30
—
—
ns
t
extrst
RESET PIN