Datasheet

Electrical Characteristics
MC9S08LG32 Series Data Sheet, Rev. 9
Freescale Semiconductor 31
2.11.3 SPI Timing
Table 16 and Figure 23 through Figure 26 describe the timing requirements for the SPI system.
Table 16. SPI Timing
No. C Function Symbol Min Max Unit
— D Operating frequency
Master
Slave
f
op
f
Bus
/2048
0
f
Bus
/2
f
Bus
/4
Hz
D SPSCK period
Master
Slave
t
SPSCK
2
4
2048
—
t
cyc
t
cyc
D Enable lead time
Master
Slave
t
Lead
12
1
—
—
t
SPSCK
t
cyc
D Enable lag time
Master
Slave
t
Lag
12
1
—
—
t
SPSCK
t
cyc
D Clock (SPSCK) high or low time
Master
Slave
t
WSPSCK
t
cyc
–30
t
cyc
– 30
1024 t
cyc
—
ns
ns
D Data setup time (inputs)
Master
Slave
t
SU
15
15
—
—
ns
ns
D Data hold time (inputs)
Master
Slave
t
HI
0
25
—
—
ns
ns
D Slave access time t
a
—1t
cyc
D Slave MISO disable time t
dis
—1t
cyc
D Data valid (after SPSCK edge)
Master
Slave
t
v
—
—
25
25
ns
ns
D Data hold time (outputs)
Master
Slave
t
HO
0
0
—
—
ns
ns
D Rise time
Input
Output
t
RI
t
RO
—
—
t
cyc
– 25
25
ns
ns
D Fall time
Input
Output
t
FI
t
FO
—
—
t
cyc
– 25
25
ns
ns
1
2
3
4
5
6
7
8
9
10
11
12