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MC9S08PA60 Reference Manual

Supports: MC9S08PA60 and MC9S08PA32

Document Number: MC9S08PA60RM

Rev. 1, 9/2012

Summary of content (639 pages)

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MC9S08PA60 Reference Manual Supports: MC9S08PA60 and MC9S08PA32 Document Number: MC9S08PA60RM Rev.
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MC9S08PA60 Reference Manual, Rev. 1, 9/2012 2 Freescale Semiconductor, Inc.
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Contents Section number Title Page Chapter 1 Device Overview 1.1 Introduction.....................................................................................................................................................................33 1.2 MCU block diagram.......................................................................................................................................................34 1.3 System clock distribution.......................................................
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Section number 3.3 Title Page 3.2.5 LVD enabled in stop mode..............................................................................................................................53 3.2.6 Power modes behaviors...................................................................................................................................53 Low voltage detect (LVD) system...........................................................................................................................
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Section number 4.6 Title Page 4.5.2.7 Security..........................................................................................................................................87 4.5.2.8 Flash and EEPROM commands.....................................................................................................89 4.5.2.9 Flash and EEPROM command summary......................................................................................91 Flash and EEPROM registers descriptions..........
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Section number 5.2.1.2 5.3 Page Edge and level sensitivity..............................................................................................................125 Interrupt pin request register...........................................................................................................................................125 5.3.1 5.4 Title Interrupt Pin Request Status and Control Register (IRQ_SC).........................................................................
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Section number 6.6 Title Page System Control Registers................................................................................................................................................137 6.6.1 System Reset Status Register (SYS_SRS).......................................................................................................137 6.6.2 System Background Debug Force Reset Register (SYS_SBDFR)..................................................................139 6.6.
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Section number Title Page 7.7.2 Port B Data Register (PORT_PTBD)..............................................................................................................157 7.7.3 Port C Data Register (PORT_PTCD)..............................................................................................................157 7.7.4 Port D Data Register (PORT_PTDD)..............................................................................................................158 7.7.
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Section number Title Page 7.7.31 Port B Pullup Enable Register (PORT_PTBPE)..............................................................................................185 7.7.32 Port C Pullup Enable Register (PORT_PTCPE)..............................................................................................186 7.7.33 Port D Pullup Enable Register (PORT_PTDPE).............................................................................................188 7.7.
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Section number 8.3 Title Page Initialization / application information...........................................................................................................................204 8.3.1 Initializing FEI mode.......................................................................................................................................205 8.3.2 Initializing FBI mode....................................................................................................................
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Section number 9.2.2 9.3 Title Page Debug module (DBG)......................................................................................................................................221 System modules..............................................................................................................................................................222 9.3.1 Watchdog (WDOG)......................................................................................................................
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Section number 9.10.1.4 9.10.2 Title Page Temperature sensor........................................................................................................................243 Analog comparator (ACMP)............................................................................................................................244 9.10.2.1 ACMP configuration information..................................................................................................246 9.10.2.2 ACMP in stop3 mode.
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Section number 10.3.7 Title Page 10.3.6.5 Indexed, 16-Bit Offset (IX2)..........................................................................................................259 10.3.6.6 SP-Relative, 8-Bit Offset (SP1).....................................................................................................259 10.3.6.7 SP-Relative, 16-Bit Offset (SP2)...................................................................................................260 Memory to memory Addressing Mode.
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Section number Title Page 11.4 Memory Map and Registers............................................................................................................................................281 11.4.1 KBI Status and Control Register (KBIx_SC)..................................................................................................282 11.4.2 KBIx Pin Enable Register (KBIx_PE).............................................................................................................
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Section number 12.3.9 Title Page Channel Value High (FTMx_CnVH)...............................................................................................................303 12.3.10 Channel Value Low (FTMx_CnVL)................................................................................................................304 12.3.11 Counter Initial Value High (FTMx_CNTINH)................................................................................................304 12.3.
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Section number Title Page 12.4.6 Edge-aligned PWM (EPWM) mode................................................................................................................334 12.4.7 Center-aligned PWM (CPWM) mode..............................................................................................................336 12.4.8 Combine mode.................................................................................................................................................338 12.4.8.
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Section number Title Page 12.4.20 Capture test mode.............................................................................................................................................370 12.4.21 Dual edge capture mode...................................................................................................................................371 12.4.21.1 One-shot capture mode..................................................................................................................
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Section number Title Page 13.6 Register definition...........................................................................................................................................................387 13.6.1 MTIM Status and Control Register (MTIMx_SC)..........................................................................................388 13.6.2 MTIM Clock Configuration Register (MTIMx_CLK)....................................................................................389 13.6.
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Section number Title Page 14.6 Initialization/application information.............................................................................................................................402 Chapter 15 Serial communications interface (SCI) 15.1 Introduction.....................................................................................................................................................................403 15.1.1 Features...........................................................
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Section number Title Page Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI) 16.1 Introduction.....................................................................................................................................................................425 16.1.1 Features............................................................................................................................................................425 16.1.2 Modes of Operation.....................................
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Section number 16.4.7 16.4.9 Page Error Conditions...............................................................................................................................................445 16.4.7.1 16.4.8 Title Mode Fault Error............................................................................................................................445 Low Power Mode Options........................................................................................................................
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Section number Title Page 17.3 Memory Map and Register Descriptions........................................................................................................................459 17.3.1 SPI control register 1 (SPIx_C1)......................................................................................................................459 17.3.2 SPI control register 2 (SPIx_C2)...................................................................................................................
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Section number Title Page 17.4.12 Interrupts..........................................................................................................................................................485 17.4.12.1 MODF............................................................................................................................................486 17.4.12.2 SPRF.......................................................................................................................................
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Section number Title Page 18.3.12 I2C SCL Low Timeout Register Low (I2C_SLTL).........................................................................................506 18.4 Functional description.....................................................................................................................................................506 18.4.1 I2C protocol...........................................................................................................................................
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Section number Title Page 18.5 Initialization/application information.............................................................................................................................519 Chapter 19 Analog-to-digital converter (ADC) 19.1 Introduction.....................................................................................................................................................................523 19.1.1 Features...............................................................
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Section number Title Page 19.4.4.2 Completing conversions.................................................................................................................539 19.4.4.3 Aborting conversions.....................................................................................................................539 19.4.4.4 Power control.................................................................................................................................540 19.4.4.
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Section number Title Page Chapter 20 Analog comparator (ACMP) 20.1 Introduction.....................................................................................................................................................................557 20.1.1 Features............................................................................................................................................................557 20.1.2 Modes of operation..........................................................
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Section number Title Page 21.5.4 CRC Data 3 Register (CRC_D3).....................................................................................................................569 21.5.5 CRC Polynomial 0 Register (CRC_P0)...........................................................................................................569 21.5.6 CRC Polynomial 1 Register (CRC_P1)...........................................................................................................570 21.5.
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Section number 22.3.2 Title Page 22.3.1.2 Refreshing the Watchdog...............................................................................................................584 22.3.1.3 Example code: Refreshing the Watchdog......................................................................................585 Configuring the Watchdog...............................................................................................................................585 22.3.2.
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Section number 23.3.6 Title Page Hardware breakpoints......................................................................................................................................604 23.4 Memory map and register description............................................................................................................................605 23.4.1 BDC Status and Control Register (BDC_SCR)...............................................................................................
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Section number Title Page 24.3.16 Debug Count Status Register (DBG_CNT).....................................................................................................627 24.4 Functional description.....................................................................................................................................................628 24.4.1 24.4.2 Comparator...............................................................................................................................
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MC9S08PA60 Reference Manual, Rev. 1, 9/2012 32 Freescale Semiconductor, Inc.
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Chapter 1 Device Overview 1.1 Introduction These devices are members of the low-cost, high-performance HCS08 family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 central processor unit and are available with a variety of modules, memory sizes and types, and package types. The following table summarizes the peripheral availability per package type for the devices available. Table 1-1.
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MCU block diagram Table 1-2. Feature availability (continued) Pin number 64-pin 48-pin 44-pin XOSC Yes RTC Yes FTM0 channels 2-ch FTM1 channels 2-ch FTM2 channels 6-ch MTIM0 Yes MTIM1 Yes SPI0 (8-bit) Yes SPI1 (16-bit) Yes IIC Yes ACMP Yes SCI0 Yes SCI1 Yes SCI2 Yes 32-pin No ADC channels 16 12 12 12 KBI pins 16 16 12 12 GPIO 57 41 37 28 1.2 MCU block diagram The block diagram below shows the structure of the MCUs. MC9S08PA60 Reference Manual, Rev.
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Port A Port B PTB0/KBI0P4/RxD0/ADP4 PTB1/KBI0P5/TxD0/ADP5 PTB2/KBI0P6/SPSCK0/ADP6 PTB3/KBI0P7/MOSI0/ADP7 3 PTB4/FTM2CH4/MISO0 3 PTB5/FTM2CH5/SS0 PTB6/SDA/XTAL PTB7/SCL/EXTAL Port C MODULE (KBI0) PTC0/FTM2CH0/ADP8 PTC1/FTM2CH1/ADP9/ PTC2/FTM2CH2/ADP10 PTC3/FTM2CH3/ADP11 PTC4/FTM1CH0/RTCO PTC5/FTM1CH1 PTC6/RxD1 PTC7/TxD1 Port D BDC PTD0/KBI1P0/FTM2CH2/SPSCK1 3 PTD1/KBI1P1/FTM2CH3/MOSI1 PTD2/KBI1P2/MISO1 PTD3/KBI1P3/SS1 PTD4/KBI1P4 PTD5/KBI1P5 PTD6/KBI1P6/RxD2 PTD7/KBI1P7/TxD2 Port E CPU PTE0/SPSCK0/
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System clock distribution 1.3 System clock distribution These series contain three on-chip clock sources: • Internal clock source (ICS) module — The main clock source generator providing bus clock and other reference clocks to peripherals • External oscillator (XOSC) module — The external oscillator providing reference clock to internal clock source (ICS), the real-time clock counter clock module (RTC) and other MCU sub-systems.
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Chapter 1 Device Overview • ICSCLK(BUS) — This up to 20 MHz clock source is used as the bus clock that is the reference to CPU and all peripherals.
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System clock distribution MC9S08PA60 Reference Manual, Rev. 1, 9/2012 38 Freescale Semiconductor, Inc.
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Chapter 2 Pins and connections MC9S08PA60 Reference Manual, Rev. 1, 9/2012 Freescale Semiconductor, Inc.
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Device pin assignment PTE3/SS0 PTC6/RxD1 PTC7/TxD1 PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1 52 51 50 49 PTE2/MISO0 54 53 PTG2 PTG3 PTG1 55 PTG0 58 57 56 PTE0/SPSCK0/TCLK11 PTE1/MOSI01 PTC5/FTM1CH1 59 PTC4/FTM1CH0/RTCO 62 61 60 PTA4/ACMPO/BKGD/MS PTA5/IRQ/TCLK0/RESET 64 63 2.
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PTE3/SS0 PTC6/RxD1 PTC7/TxD1 PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1 40 39 38 37 PTE2/MISO0 42 41 PTE0/SPSCK0/TCLK11 PTE1/MOSI01 PTC5/FTM1CH1 45 43 PTC4/FTM1CH0 46 44 PTA4/ACMPO/BKGD/MS PTA5/IRQ/TCLK0/RESET 47 48 Chapter 2 Pins and connections 34 PTD2/KBI1P2/MISO1 PTH2/BUSOUT 4 33 PTD3/KBI1P3/SS1 VDD 5 32 PTD4/KBI1P4 VDDA /VREFH 6 31 VDD 7 30 VSS 8 29 PTE4 9 PTB7/SCL/EXTAL PTB6/SDA/XTAL 10 28 PTA6/FTM2FAULT1/ADP2 17 18 PTC2/FTM2CH2/ADP10 P
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PTC6/RxD1 PTC7/TxD1 PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA1/KBI0P1/FTM1CH0/ACMP1/ADP1 36 35 34 PTE2/MISO0 38 37 PTE0/SPSCK0/TCLK11 PTE1/MOSI01 PTC5/FTM1CH1 41 39 PTC4/FTM1CH0 42 40 PTA4/ACMPO/BKGD/MS PTA5/IRQ/TCLK0/RESET 43 44 Device pin assignment PTD1/KBI1P1/FTM2CH3/MOSI1 1 1 33 PTA2/KBI0P2/RxD0/SDA2 PTD0/KBI1P0/FTM2CH2/SPSCK1 1 2 32 3 31 PTA3/KBI0P3/TxD0/SCL2 PTE7/TCLK2 PTH2/BUSOUT 4 30 PTD3/KBI1P3/SS1 VDD 5 29 PTD4/KBI1P4 VDDA /VREFH VSSA /V REFL VSS 6 28 7 27 8
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PTC6/RxD1 PTC7/TxD1 PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0 PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1 26 25 PTC5/FTM1CH1 29 27 PTC4/FTM1CH0 30 28 PTA4/ACMPO/BKGD/MS PTA5/IRQ/TCLK0/RESET 32 31 Chapter 2 Pins and connections PTD1/KBI1P1/FTM2CH3/MOSI1 1 1 24 PTA2/KBI0P2/RxD0/SDA2 PTD0/KBI1P0/FTM2CH2/SPSCK1 1 2 23 PTA3/KBI0P3/TxD0/SCL2 PTD2/KBI1P2/MISO1 3 22 VDDA /VREFH 4 21 PTD3/KBI1P3/SS1 VSSA /V 5 20 PTA6/FTM2FAULT1/ADP2 PTA7/FTM2FAULT2/ADP3 VDD REFL 15 16 14 PTC0/FTM2CH0/ADP8 PTB3/KBI0P7/MO
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Pin functions Typically, application systems have two separate capacitors across the power pins. In this case, there should be a bulk electrolytic capacitor, such as a 10 µF tantalum capacitor, that provides bulk charge storage for the overall system and a 0.1 µF ceramic bypass capacitor located as near to the paired VDD and VSS power pins as practical to suppress high-frequency noise. MCU Vss VDD C1 0.1 F C2 VDD Figure 2-5. Power supply bypassing 2.2.
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Chapter 2 Pins and connections 2.2.3 Oscillator (XTAL, EXTAL) The XTAL and EXTAL pins are used to provide the connections for the on-chip oscillator. The oscillator (XOSC) in this MCU is a Pierce oscillator that can accommodate a crystal or ceramic resonator. Optionally, an external clock source can be connected to the EXTAL input pin. The oscillator can be configured to run in stop3 mode.
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Pin functions 2.2.4 External reset pin (RESET) A low on the RESET pin forces the MCU to an known startup state. RESET is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. This pin contains an internal pullup resistor. 2.2.5 Background/mode select (BKGD/MS) During a power-on-reset (POR) or background debug force reset, the PTA4/ACMPO/ BKGD/MS pin functions as a mode select pin.
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Chapter 2 Pins and connections PTA5/IRQ/TCLK0/RESET Optional Manual Reset BKGD/MS VSS V DD Figure 2-8. Typical debug circuit 2.2.6 Port A input/output (I/O) pins (PTA–PTA0) PTA–PTA0 except PTA4 are general-purpose, bidirectional I/O port pins. These port pins also have selectable pullup devices when configured for input mode except PTA4, the pullup devices are selectable on an individual port bit basis.
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Pin functions NOTE When configuring IIC to use SDA(PTA2) and SCL(PTA3) pins, if an application uses internal pullups instead of external pullups, the internal pullups remain present setting when the pins are configured as outputs, but they are automatically disabled to save power when the output values are low. 2.2.10 High current drive pins (PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0, PTH1) When high current function is enabled, PTB4, PTB5, PTD0, PTD1, PTE0, PTE1, PTH0 and PTH1 can drive output current.
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Chapter 2 Pins and connections Table 2-1.
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Pin functions Table 2-1.
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Chapter 3 Power management 3.1 Introduction The operating modes of the device are described in this chapter. Entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.
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Features 3.2.2 Wait mode Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine.
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Chapter 3 Power management 3.2.4 Active BDM enabled in stop3 mode Entry into the active background mode from run mode is enabled if the BDC_SCR[ENBDM] bit is set. This register is described in the development support. If BDC_SCR[ENBDM] is set when the CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode, so background debug communication is still possible.
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Low voltage detect (LVD) system Table 3-1. Low power mode behavior (continued) Mode Run Wait Stop3 RAM On Standby Standby ADC On On Optional on ACMP On On Optional on I/O On On States held SCI On On Standby SPI On On Standby IIC On On Standby FTM On On Standby MTIM On On Standby WDOG On On Optional on DBG On On Standby IPC On On Standby CRC On On Standby RTC On On Optional on LVD On On Optional on 3.
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Chapter 3 Power management vDD LVDV:LVDWV R1 LVD0 + LVD1 LVD LVW0 LVW1 LVW2 LVW3 + LVW vBG Bandgap R7 vss Figure 3-1. Low voltage detect (LVD) block diagram 3.3.1 Power-on reset (POR) operation When power is initially applied to the MCU, or when the supply voltage drops below the VPOR level, the POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the chip in reset until the supply has risen above the VLVDL level.
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Bandgap reference 3.4 Bandgap reference This device includes an on-chip bandgap reference (≈1.2V) connected to ADC channel and ACMP. The bandgap reference voltage will not drop under the full operating voltage even when the operating voltage is falling. This reference voltage acts as an ideal reference voltage for accurate measurements. 3.
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Chapter 3 Power management PMC_SPMSC1 field descriptions (continued) Field Description NOTE: LVWF will be set in the case when VSupply transitions below the trip point or after reset and VSupply is already below VLVW. LVWF bit may be 1 after power on reset, therefore, to use LVW interrupt function, before enabling LVWIE, LVWF must be cleared by writing LVWACK first. 0 1 6 LVWACK 5 LVWIE Low-Voltage Warning Acknowledge If LVWF = 1, a low-voltage condition has occurred.
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Power management control bits and registers 3.5.2 System Power Management Status and Control 2 Register (PMC_SPMSC2) This register is used to report the status of the low-voltage warning function, and to configure the stop mode behavior of the MCU. This register should be written during the user's reset initialization program to set the desired controls, even if the desired settings are the same as the reset settings.
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Chapter 4 Memory map 4.1 Memory map The HCS08 core processor can address 64 KB of memory space.
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Reset and interrupt vector assignments 0x0000 0x003F 0x0040 0x0000 0x003F 0x0040 DIRECT PAGE REGISTERS RAM 4,096 BYTES 4096 BYTES RAM 0x103F 0x103F 0x1040 8,128 BYTES FLASH 0x2FFF 0x3000 0x30FF 0x3100 0x31FF 0x3200 DIRECT PAGE REGISTERS UNIMPLEMENTED 0x3000 0x30FF 0x3100 0x31FF HIGH PAGE REGISTERS 256 BYTES EEPROM HIGH PAGE REGISTERS 256 BYTES EEPROM UNIMPLEMENTED 0x8000 52,736B FLASH 32,768B FLASH 0xFFAF 0xFFB0 0xFFFF 0xFFAF 0xFFB0 0xFFFF VECTOR TABLE VECTOR TABLE MC9S08PA32 MC9S08PA60 Fi
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Chapter 4 Memory map Table 4-1.
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Register addresses and bit assignments Table 4-2.
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Chapter 4 Memory map • Direct-page registers are located in the first 64 locations in the memory map, so they can be accessed with efficient direct addressing mode instructions. • High-page registers are used much less often, so they are located above 0x3000 in the memory map. This leaves room in the direct page for more frequently used registers and variables. Direct-page registers can be accessed with efficient direct addressing mode instructions.
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Register addresses and bit assignments Table 4-3.
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Chapter 4 Memory map Table 4-4.
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Register addresses and bit assignments Table 4-4.
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Chapter 4 Memory map Table 4-4.
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Register addresses and bit assignments Table 4-4.
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Chapter 4 Memory map Table 4-4.
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Register addresses and bit assignments Table 4-4.
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Chapter 4 Memory map Table 4-4.
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Random-access memory (RAM) Table 4-5.
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Chapter 4 Memory map The RAM retains data when the MCU is in low-power wait,or stop3 mode. At power-on, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided that the supply voltage does not drop below the minimum value for RAM retention. For compatibility with older M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF.
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Flash and EEPROM memory while commands are being executed on EEPROM memory. It is not possible to read from EEPROM memory while a command (erase/program) is executing on flash memory. Simultaneous EEPROM memory are implemented with error correction codes (ECC) that can resolve single bit faults and detect double bit faults. The following figure shows the block diagram of the flash and EEPROM module.
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Chapter 4 Memory map • Protection scheme to prevent accidental program or erase of EEPROM memory • Ability to program up to four bytes in a burst sequence Other features • No external high-voltage power supply required for flash memory program and erase operations • Interrupt generation on flash command completion and flash error detection • Security mechanism to prevent unauthorized access to the flash memory 4.5.2 Function descriptions 4.5.2.
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Flash and EEPROM Table 4-6. Flash memory addressing Device Global address Size (Bytes) Description User availability Sector [0:7]: N/A MC9S08PA60 0x0000 — 0xFFFF 64 KB Sector [8]: Last 448 bytes available Flash block contains Sector [9:23]: fully available flash configuration field Sector [24]: N/A 32 KB Flash block contains Sector [64:127]: fully available flash configuration field Sector [25:127]: fully available MC9S08PA32 0x8000 — 0xFFFF 4.5.2.
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Chapter 4 Memory map 3. Execute valid flash and EEPROM commands according to MCU functional mode and MCU security state. The figure below shows a general flowchart of the flash or EEPROM command write sequence. MC9S08PA60 Reference Manual, Rev. 1, 9/2012 Freescale Semiconductor, Inc.
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Flash and EEPROM START Read: FCLKDIV register Clock Divider Value Check No FDIV Correct? Read: FSTAT register Yes Read: FSTAT register FCCOB Availability Check CCIF Set? No NOTE: FCLKDIV must be set after each reset Yes No CCIF Set? Write: FCLKDIV register Yes ACCERR Access Error and or FPVIOL Set? Protection Violation Check No Results from previous Command Yes Write: FSTAT register Clear ACCERR FPVIOL 0x30 Write to FCCOBIX register to identify specific command parameter to load Write
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Chapter 4 Memory map 4.5.2.4.1 Writing the FCLKDIV register Prior to issuing any flash and EEPROM program or erase command after a reset, the user is required to write the FCLKDIV register to divide BUSCLK down to a target FCLK of 1MHz. The following table shows recommended values for the FDIV field based on BUSCLK frequency. Table 4-7. FDIV values for various BUSCLK frequencies BUSCLK frequency FDIV[5:0] (MHz) MIN1 MAX2 1.0 1.6 0x00 1.6 2.6 0x01 2.6 3.6 0x02 3.6 4.6 0x03 4.6 5.
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Flash and EEPROM When the FCLKDIV register is written, the FCLKDIV[FDIVLD] bit is set automatically. If the FCLKDIV[FDIVLD] bit is 0, the FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written, any flash and EEPROM program or erase command loaded during a command write sequence will not execute and the FSTAT[ACCERR] bit will be set. 4.5.2.4.
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Chapter 4 Memory map Table 4-8.
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Flash and EEPROM Table 4-9. Flash and EEPROM commands by mode and security state (continued) Unsecured Secured U1 U2 Set user margin level * N/A 0x10 Erase verify EEPROM section * * 0x11 Program EEPROM * N/A 0x12 Erase EEPROM sector * N/A FCMD Command 0x0D 1. Unsecured User mode 2. Secured User mode 4.5.2.
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Chapter 4 Memory map Flash and EEPROM Command Complete Interrupt Request CCIE CCIF CPU Interrupt DFDIE DFDIF Flash and EEPROM Error Interrupt Request SFDIE SFDIF Figure 4-4. Flash and EEPROM module interrupts implementation 4.5.2.6 Protection The FPROT register can be set to protect regions in the flash memory from accidental programing or erasing.
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Flash and EEPROM Default protection settings as well as security information that allows the MCU to restrict access to the flash module are stored in the flash configuration field as described in the table below. Table 4-11. Flash configuration field Global address Size (Bytes) Description 0xFF70 — 0xFF771 8 Backdoor comparison key. See Verify backdoor access key command and Unsecuring the MCU using backdoor key access.
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Chapter 4 Memory map FPHDIS = 1 FPLDIS = 1 FPHDIS = 1 FPLDIS = 0 FPHDIS = 0 FPLDIS = 1 FPHDIS = 0 FPLDIS = 0 Scenario 7 Scenario 6 Scenario 5 Scenario 4 FPOPEN = 1 FPOPEN = 1 FPOPEN = 1 FPOPEN = 1 Flash Start Address 0x8000 FPLS[1:0] FPHS[1:0] 0xFFFF Scenario 3 Scenario 2 Scenario 1 Scenario 0 FPOPEN = 0 FPOPEN = 0 FPOPEN = 0 FPOPEN = 0 Flash Start Address 0x8000 FPLS[1:0] FPHS[1:0] 0xFFFF Unprotected region Protected region with size defined by FPLS Protected region not defined
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Flash and EEPROM Table 4-13. Flash protection scenario transitions To protection scenario From protection scenario 0 1 2 3 0 × × × × 1 × 2 4 × 4 × × × × × × × × 7 × × × × 7 × 3 6 6 × × 5 5 × × × × × × The flash protection address range is listed in the following two tables regarding the scenarios in the table above. Table 4-14.
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Chapter 4 Memory map Table 4-16. EEPROM protection address range (continued) DPS[2:0] Global address range Protected size 011 0x3100 – 0x317F 128 bytes 100 0x3100 – 0x319F 160 bytes 101 0x3100 – 0x31BF 192 bytes 110 0x3100 – 0x31DF 224 bytes 111 0x3100 – 0x31FF 256 bytes All possible flash protection scenarios are shown in Figure 4-6. Although the protection scheme is loaded from the flash memory at global address 0xFF7C during the reset sequence, it can be changed by the user. 4.5.2.
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Flash and EEPROM the flash and EEPROM memory, the FSEC[SEC] bits will be changed to unsecure the MCU. Key values of 0x0000 and 0xFFFF are not permitted as backdoor keys. While the Verify Backdoor Access Key command is active, flash memory and EEPROM memory will not be available for read access and will return invalid data. The user code stored in the flash memory must have a method of receiving the backdoor keys from an external stimulus.
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Chapter 4 Memory map 3. Configure registers NVM_FERSTAT and NVM_FPROT to disable protection in the flash and EEPROM memory. 4. Execute the erase all blocks command write sequence to erase the flash and EEPROM memory. Alternately, the unsecure NVM command can be executed. If the flash and EEPROM memory are verified as erased, the MCU will be unsecured. All BDM. commands will now be enabled and the flash security byte may be programmed to the unsecure state by continuing with the steps that follow. 5.
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Flash and EEPROM Table 4-17.
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Chapter 4 Memory map 4.5.2.8.3 Allowed simultaneous flash and EEPROM operations Only the operations marked 'OK' in the following table are permitted to be run simultaneously on the flash and EEPROM blocks. Some operations cannot be executed simultaneously because certain hardware resources are shared by the two memories. The priority has been placed on permitting flash reads while program and erase operations execute on the EEPROM, providing read (flash) while write (EEPROM) functionality. Table 4-19.
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Flash and EEPROM CAUTION An EEPROM byte or flash longword must be in the erased state before being programmed. Cumulative programming of bits within an EEPROM byte or flash longword is not allowed. 4.5.2.9.1 Erase verify all blocks command The erase verify all blocks command will verify that all flash and EEPROM blocks have been erased. Table 4-20.
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Chapter 4 Memory map 1. Global address [23] selects between flash (0) or EEPROM (1) block, that can otherwise eventually share the same address on the MCU global memory map. Upon clearing NVM_FSTAT[CCIF] to launch the erase verify block command, the memory controller will verify that the selected flash or EEPROM block is erased. The NVM_FSTAT[CCIF] flag will set after the erase verify block operation has completed.
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Flash and EEPROM Table 4-25.
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Chapter 4 Memory map Table 4-27. Read once command error handling Register Error bit Error condition Set if CCOBIX[2:0] != 001 at command launch ACCERR Set if an invalid phrase index is supplied FSTAT 4.5.2.9.
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Flash and EEPROM Table 4-29. Program flash command error handling Register Error bit Error condition Set if CCOBIX[2:0] ≠ 011 or 101 at command launch Set if command not available in current mode (see Table 4-9) ACCERR NVM_FSTAT Set if an invalid global address [23:0] is supplied (see Table 4-6)1 Set if a misaligned longword address is supplied (global address [1:0] != 00) Set if the requested group of words breaches the end of the flash block.
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Chapter 4 Memory map The reserved nonvolatile information register accessed by the program once command cannot be erased, and any attempt to program one of these phrases a second time will not be allowed. Valid phrase index values for the program once command range from 0x0000 to 0x0007. During execution of the program once command, any attempt to read addresses within flash will return invalid data. Table 4-31.
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Flash and EEPROM Table 4-33. Erase all blocks command error handling Register Error bit ACCERR NVM_FSTAT FPVIOL Error condition Set if CCOBIX[2:0] ≠ 000 at command launch Set if command not available in current mode (see Table 4-9) Set if any area of the flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation1 MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation1 1. As found in the memory map for NVM 4.
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Chapter 4 Memory map Table 4-36. Erase flash sector command FCCOB requirements CCOBIX[2:0] FCCOB parameters 000 0x0A Global address [23:16] to identify flash block to be erased Global address [15:0] anywhere within the sector to be erased. Refer to Overview for the flash sector size 001 Upon clearing FSTAT[CCIF] to launch the erase flash sector command, the memory controller will erase the selected flash sector and then verify that it is erased.
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Flash and EEPROM Table 4-39. Unsecure flash command error handling Register Error bit ACCERR FSTAT FPVIOL Error condition Set if CCOBIX[2:0] != 000 at command launch Set if command is not available in current mode (see Table 4-9) Set if any area of the flash or EEPROM memory is protected MGSTAT1 Set if any errors have been encountered during the verify operation1 MGSTAT0 Set if any non-correctable errors have been encountered during the verify operation1 1. As found in the memory map for NVM 4.5.
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Chapter 4 Memory map Table 4-41. Verify backdoor access key command error handling Register Error bit Error condition Set if CCOBIX[2:0] ≠ 100 at command launch ACCERR NVM_FSTAT 4.5.2.9.
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Flash and EEPROM Table 4-43. Valid set user margin level settings CCOB Level description (CCOBIX = 010) 0x0000 Return to normal level 0x0001 User margin-1 level1 0x0002 User margin-0 level2 1. Read margin to the erased state 2. Read margin to the programmed state Table 4-44.
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Chapter 4 Memory map Upon clearing NVM_FSTAT[CCIF] to launch the erase verify that EEPROM section command, the memory controller will verify the selected section of EEPROM memory is erased. The NVM_FSTAT[CCIF] flag will set after the erase verify EEPROM section operation has completed. If the section is not erased, which means that blank check failed, both NVM_FSTAT[MGSTAT] bits will be set. Table 4-46.
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Flash and EEPROM Upon clearing NVM_FSTAT[CCIF] to launch the program EEPROM command, the user-supplied words will be transferred to the memory controller and be programmed if the area is unprotected. The CCOBIX index value at program EEPROM command launch determines how many bytes will be programmed in the EEPROM block. The NVM_FSTAT[CCIF] flag is set when the operation has completed. Table 4-48.
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Chapter 4 Memory map Table 4-50.
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Flash and EEPROM registers descriptions NOTE The FCLKDIV register must not be written while a flash command is executing (NVM_FSTAT[CCIF] = 0) Address: 3020h base + 0h offset = 3020h Bit Read 7 6 FDIVLD Write Reset 5 4 3 FDIVLCK 0 0 2 1 0 0 0 0 FDIV 0 0 0 NVM_FCLKDIV field descriptions Field Description 7 FDIVLD Clock Divider Loaded 6 FDIVLCK Clock Divider Locked 5–0 FDIV 0 1 0 1 FCLKDIV register has not been written since the last reset.
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Chapter 4 Memory map NVM_FSEC field descriptions Field 7–6 KEYEN Description Backdoor Key Security Enable Bits The KEYEN[1:0] bits define the enabling of backdoor key access to the flash module. NOTE: 01 is the preferred KEYEN state to disable backdoor key access. 00 01 10 11 5–2 Reserved 1–0 SEC Disabled Disabled Enabled Disabled This field is reserved. Flash Security Bits The SEC[1:0] bits define the security state of the MCU.
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Flash and EEPROM registers descriptions 4.6.4 Flash Configuration Register (NVM_FCNFG) The FCNFG register enables the flash command complete interrupt and forces ECC faults on flash array read access from the CPU.
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Chapter 4 Memory map 4.6.5 Flash Error Configuration Register (NVM_FERCNFG) The FERCNFG register enables the flash error interrupts for the FERSTAT flags. Address: 3020h base + 5h offset = 3025h Bit Read Write Reset 7 6 5 4 3 2 0 0 0 0 0 0 0 1 0 DFDIE SFDIE 0 0 NVM_FERCNFG field descriptions Field 7–2 Reserved 1 DFDIE Description This field is reserved. This read-only field is reserved and always has the value 0.
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Flash and EEPROM registers descriptions NVM_FSTAT field descriptions (continued) Field Description 0 1 Flash command in progress. Flash command has completed. 6 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 5 ACCERR Flash Access Error Flag The ACCERR bit indicates an illegal access has occurred to the flash memory caused by either a violation of the command write sequence or issuing an illegal flash command.
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Chapter 4 Memory map NVM_FERSTAT field descriptions Field 7–2 Reserved 1 DFDIF Description This field is reserved. This read-only field is reserved and always has the value 0. Double Bit Fault Detect Interrupt Flag The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data bits during a flash array read operation or that a flash array read operation returning invalid data was attempted on a flash block that was under a flash command operation.
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Flash and EEPROM registers descriptions Trying to alter data in any protected area in the flash memory will result in a protection violation error and the FPVIOL bit will be set in the FSTAT register. The block erase of a flash block is not possible if any of the flash sectors contained in the same flash block are protected.
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Chapter 4 Memory map 4.6.9 EEPROM Protection Register (NVM_EEPROT) The EEPROT register defines which EEPROM sectors are protected against program and erase operations. The unreserved bits of the EEPROT register are writable with the restriction that protection can be added but not removed. Writes must increase the DPS value and the DPOPEN bit can only be written from 1, protection disabled, to 0, protection enabled. If the DPOPEN bit is set, the state of the DPS bits is irrelevant.
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Flash and EEPROM registers descriptions 4.6.10 Flash Common Command Object Register:High (NVM_FCCOBHI) The FCCOB is an array of six words addressed via the CCOBIX index found in the FCCOBIX register. Byte-wide reads and writes are allowed to the FCCOB register.
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Chapter 4 Memory map Address: 3020h base + Ch offset = 302Ch Bit 7 6 5 4 Read 3 2 1 0 x* x* x* x* NV Write Reset x* x* x* x* * Notes: • x = Undefined at reset. NVM_FOPT field descriptions Field 7–0 NV Description Nonvolatile Bits The NV[7:0] bits are available as nonvolatile bits. During the reset sequence, the FOPT register is loaded from the flash nonvolatile byte in the flash configuration field at global address 0xFF7E located in flash memory. MC9S08PA60 Reference Manual, Rev.
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Flash and EEPROM registers descriptions MC9S08PA60 Reference Manual, Rev. 1, 9/2012 116 Freescale Semiconductor, Inc.
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Chapter 5 Interrupt 5.1 Interrupts Interrupts save the current CPU status and registers, execute an interrupt service routine (ISR), and then restore the CPU status so that processing resumes where it left off before the interrupt. Other than the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events such as an edge on the IRQ pin or a timeroverflow event. The debug module can also generate an SWI under certain circumstances.
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Interrupts entry to the ISR. In rare cases, the I bit may be cleared inside an ISR, after clearing the status flag that generated the interrupt, so that other interrupts can be serviced without waiting for the first service routine to finish. This practice is recommended only for the most experienced programmers because it can lead to subtle program errors that are difficult to debug.
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Chapter 5 Interrupt UNSTACKING ORDER TOWARD LOWER ADDRESSES 7 0 5 1 4 2 3 3 * X) INDEX REGISTER (LOW BYTE 2 4 PROGRAM COUNTER HIGH 1 5 PROGRAM COUNTER LOW CONDITION CODE REGISTER SP AFTER INTERRUPT STACKING ACCUMULATOR STACKING ORDER SP BEFORE THE INTERRUPT TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt stack frame When an RTI instruction executes, these values are recovered from the stack in reverse order.
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Interrupts 5.1.3 Hardware nested interrupt This device has interrupt priority controller (IPC) module to provide up to four-level nested interrupt capability. IPC includes the following features: • Four-level programmable interrupt priority for each interrupt source. • Support for prioritized preemptive interrupt service routines • Low-priority interrupt requests are blocked when high-priority interrupt service routines are being serviced.
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Chapter 5 Interrupt Inputs Outputs INTIN0 INTOUT0 + v ILR0[1:0] INTIN1 INTOUT1 ILR1[1:0] . . . v + . . . . . . . . . INTOUT47 INTIN47 ILR0 . . .
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Interrupts 5.1.3.1 Interrupt priority level register This set of registers is associated with the interrupt sources to the HCS08 CPU. Each interrupt priority level is a 2-bit value such that a user can program the interrupt priority level of each source to priority 0, 1, 2, or 3. Level 3 has the highest priority while level 0 has the lowest. Software can read or write to these registers at any time.
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Chapter 5 Interrupt 5.1.3.4 Integration and application of the IPC All interrupt inputs that comes from peripheral modules are synchronous signals. None of the asynchronous signals of the interrupts are routed to IPC. The asynchronous signals of the interrupts are routed directly to SIM module to wake system clocks in stop3 mode. Additional care must be exercised when IRQ is reprioritized by IPC. CPU instructions BIL and BIH need input from IRQ pin.
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IRQ 5.2.1 Features Features of the IRQ module include: • A Dedicated External Interrupt Pin • IRQ Interrupt Control Bits • Programmable Edge-only or Edge and Level Interrupt Sensitivity • Automatic Interrupt Acknowledge • Internal pullup device A low level applied to the external interrupt request (IRQ) pin can latch a CPU interrupt request.
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Chapter 5 Interrupt 5.2.1.1 Pin configuration options The IRQ pin enable control bit (IRQSC[IRQPE]) must be 1 for the IRQ pin to act as the IRQ input. The user can choose the polarity of edges or levels detected (IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD), or whether an event causes an interrupt or only sets the IRQF flag, which can be polled by software. When enabled, the IRQ pin defaults to use an internal pullup device (IRQSC[IRQPDD] = 0).
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Interrupt pin request register 5.3.1 Interrupt Pin Request Status and Control Register (IRQ_SC) This direct page register includes status and control bits, which are used to configure the IRQ function, report status, and acknowledge IRQ events. Address: 3Bh base + 0h offset = 3Bh Bit 7 Read 0 6 Write Reset 0 5 4 IRQPDD IRQEDG IRQPE 0 0 0 3 2 IRQF 0 IRQACK 0 0 1 0 IRQIE IRQMOD 0 0 IRQ_SC field descriptions Field Description 7 Reserved This field is reserved.
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Chapter 5 Interrupt IRQ_SC field descriptions (continued) Field 1 IRQIE Description IRQ Interrupt Enable This read/write control bit determines whether IRQ events generate an interrupt request. 0 1 0 IRQMOD Interrupt request when IRQF set is disabled (use polling). Interrupt requested whenever IRQF = 1. IRQ Detection Mode This read/write control bit selects either edge-only detection or edge-and-level detection. 0 1 IRQ event on falling/rising edges only.
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Interrupt priority control register 5.4.1 IPC Status and Control Register (IPC_SC) This register contains status and control bits for the IPC. Address: 3Eh base + 0h offset = 3Eh Bit Read Write Reset 7 IPCE 0 6 5 4 3 2 0 PSE PSF 0 0 1 IPM PULIPM 0 1 0 0 0 0 0 0 IPC_SC field descriptions Field 7 IPCE Description Interrupt Priority Controller Enable This bit enables/disables the interrupt priority controller module. 0 1 6 Reserved Disables IPCE.
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Chapter 5 Interrupt IPC_SC field descriptions (continued) Field Description IPMPS register. Writing IPM with PULIPM setting when IPCE is already set, the IPM will restore the value pulled from the IPMPS register, not the value written to the IPM register. 5.4.2 Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS) This register is used to store the previous interrupt priority mask level temporarily when the currently active interrupt is executed.
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Interrupt priority control register IPC_ILRSn field descriptions Field Description 7–6 ILRn3 Interrupt Level Register for Source n*4+3 5–4 ILRn2 Interrupt Level Register for Source n*4+2 3–2 ILRn1 Interrupt Level Register for Source n*4+1 1–0 ILRn0 Interrupt Level Register for Source n*4+0 This field sets the interrupt level for interrupt source n*4+3. This field sets the interrupt level for interrupt source n*4+2. This field sets the interrupt level for interrupt source n*4+1.
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Chapter 6 System control 6.1 System device identification (SDID) This device is hard coded to the value 0x0040 in SDID registers. 6.2 Universally unique identification (UUID) This device contains up to 64-bit UUID to identify each device in this family. The intent of UUID is to enable distributed systems to uniquely identify information without significant central coordination. 6.3 Reset and system initialization Resetting the MCU provides a way to start processing from a set of known initial conditions.
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System options • Background debug forced reset • External reset pin (RESET) • Internal clock source module reset (CLK) Each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status (SRS) register. 6.4 System options 6.4.1 BKGD pin enable After POR, PTA4/ACMPO/BKGD/MS pin functions as BKGD output. The SYS_SOPT1[BKGDPE] bit must be set to enable the background debug mode pin enable function.
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Chapter 6 System control 6.4.5 IIC pins reassignments After POR reset, IIC module pinouts of SDA and SCL are mapped on PTA2 and PTA3. SYS_SOPT1[IICPS] bit enables to reassign the IIC pinout pair on PTB6 and PTB7 respectively. Please note the PTA2 and PTA3 operate as true open drain, which can support different level IIC communication. When PTB6 and PTB7 act as IIC pins, the remote IIC level is limited to no more than MCU VDD. 6.4.
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System interconnection ACIC RTCC FTM1 ovf RTC SCI0 00 ADC trg ovf 01 MTIM0 10 11 FTM0 0 ovf ICSCLK ADHWT DELAY 1 1 2N RXDFE ch0 ch1 rxd + 1 – 0 txd PTB0/KBI0P4/RxD0/ADP4 0 1 ch0 ch1 inittrg fault0 matchtrg fault1 fault2 FTM2 fault3 trigger0 trigger1 trigger2 BUSREF PTB1/KBI0P5/TxD0/ADP5 FTMSYNC PTA6/FTM2FAULT1/ADP2 PTA7/FTM2FAULT2/ADP3 RXDCE TXDME CLKOE PTH2/BUSOUT Figure 6-1. System interconnection diagram 6.5.
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Chapter 6 System control TXD0 SCI0 0 PTB1/KBI0P5/TXD0/ADP5 1 FTM0CH0 PORT LOGIC TXDME Figure 6-2. IR modulation diagram 6.5.3 SCI0 RxD capture RxD0 pin is selectable connected to SCI0 module directly or tagged to FTM0 channel 1. When SYS_SOPT2[RXDCE] bit is set, the RxD0 pin is connected to both SCI0 and FTM0 channel 1, and the FTM0CH1 pin is released to other shared functions. When this bit is clear, the RxD0 pin is connected to SCI0 only. RxD0 RxD0 SCI0 FTM0 CH1 RXDCE Figure 6-3.
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System interconnection RXD0 SCI0 0 1 ACMP0 ACMP1 + To SCI0 RxD Capture Function RXDFE From Internal or External Reference Voltage Figure 6-4. IR demodulation diagram 6.5.5 RTC capture RTC overflow may be captured by FTM1 channel 1 by setting SYS_SOPT2[RTCC] bit. When this bit is set, the RTC overflow is connected to FTM1 channel 1 for capture, the FTM1CH1 pin is released to other shared functions. 6.5.
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Chapter 6 System control When ADC hardware trigger selects the output of FTM2 triggers, an 8-bit delay block will be enabled. This logic delays any trigger from FTM2 with an 8-bit counter whose value is specified by SYS_SOPT4[DELAY] bit. The reference clock to this module is the output of ICSCLK with selectable pre-divider specified by SYS_SOPT3[BUSREF]. 6.
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System Control Registers cause the corresponding bit(s) to be set; bits corresponding to sources that are not active at the time of reset will be cleared. NOTE The RESET values in the figure are values for power on reset; for other resets, the values depend on the trigger causes.
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Chapter 6 System control SYS_SRS field descriptions (continued) Field Description 0 1 1 LVD Reset not caused by ICS module. Reset caused by ICS module. Low Voltage Detect If the LVDRE bit is set in run mode or both LVDRE and LVDSE bits are set in stop mode, and the supply drops below the LVD trip voltage, an LVD reset will occur. This bit is also set by POR. NOTE: This bit reset to 1 on POR and LVR and reset to 0 on other reset. 0 1 0 Reserved Reset not caused by LVD trip or POR.
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System Control Registers 6.6.3 System Device Identification Register: High (SYS_SDIDH) This read-only register, together with SYS_SDIDL, is included so that host development systems can identify the HCS08 derivative and revision number. This allows the development software to recognize where specific memory blocks, registers, and control bits are located in a target MCU.
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Chapter 6 System control 6.6.5 System Options Register 1 (SYS_SOPT1) Address: 3000h base + 4h offset = 3004h Bit Read Write Reset 7 6 5 4 3 2 1 0 SCI0PS SPI0PS IICPS FTM2PS BKGDPE RSTPE FWAKE STOPE 0 0 0 0 1 1 0 0 SYS_SOPT1 field descriptions Field 7 SCI0PS Description SCI0 Pin Select This write-once bit selects the SCI0 pinouts. 0 1 6 SPI0PS SPI0 Pin Select This write-once bit selects the SPI0 Pinouts. 0 1 5 IICPS This write-once bit selects the IIC port pins.
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System Control Registers SYS_SOPT1 field descriptions (continued) Field 1 FWAKE Description Fast Wakeup Enable This write once bit can set CPU wakeup without any interrupt subroutine serviced. This action saved more than 11 cycles(whole interrupt subroutine time). After wake up CPU continue the address before wait or stop.
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Chapter 6 System control SYS_SOPT2 field descriptions (continued) Field 5 RXDFE Description SCI0 RxD Filter Select This bit enables the SCI0 RxD input filtered by ACMP. When this function is enabled, any signal tagged with ACMP inputs can be regarded SCI0. 0 1 4 RXDCE SCI0 RxD Capture Select This bit enables the SCI0 RxD is captured by FTM0 channel 1. 0 1 3 ACIC This bit connects the output of ACMP to FTM1 input channel 0. ACMP output not connected to FTM1 input channel 0.
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System Control Registers SYS_SOPT3 field descriptions Field 7 DLYACT Description FTM2 Trigger Delay Active This read-only bit specifies the status if the FTM2 initial or match delay is active. This bit is set when an FTM2 trigger arrives and the delay counter is ticking. Otherwise, this bit will be clear. 0 1 6–4 Reserved 3 CLKOE This field is reserved. This read-only field is reserved and always has the value 0.
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Chapter 6 System control 6.6.9 Illegal Address Register: High (SYS_ILLAH) The SYS_ILLAH is a read-only register containing the high 8-bit of the illegal address of ILAD reset. Address: 3000h base + 4Ah offset = 304Ah Bit 7 6 5 4 Read 3 2 1 0 x* x* x* x* ADDR[15:8] Write Reset x* x* x* x* * Notes: • x = Undefined at reset.
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System Control Registers SYS_ILLAL field descriptions Field 7–0 ADDR[7:0] Description Low 8-bit of illegal address NOTE: For ILAD, it resets to the low 8-bit of the illegal address; in other cases, the reset to values are undetermined. 6.6.11 Universally Unique Identifier Register 1 (SYS_UUID1) The read-only SYS_UUIDx registers contain a series of 64-bit number to identify the unique device in the family.
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Chapter 6 System control SYS_UUID2 field descriptions Field 7–0 ID[55:48] Description Universally Unique Identifier 6.6.13 Universally Unique Identifier Register 3 (SYS_UUID3) The read-only SYS_UUIDx registers contain a series of 63-bit number to identify the unique device in the family. Address: 3000h base + FAh offset = 30FAh Bit 7 6 5 4 Read 3 2 1 0 x* x* x* x* ID[47:40] Write Reset x* x* x* x* * Notes: • x = Undefined at reset.
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System Control Registers SYS_UUID4 field descriptions Field 7–0 ID[39:32] Description Universally Unique Identifier 6.6.15 Universally Unique Identifier Register 5 (SYS_UUID5) The read-only SYS_UUIDx registers contain a series of 64-bit number to identify the unique device in the family. Address: 3000h base + FCh offset = 30FCh Bit 7 6 5 4 Read 3 2 1 0 x* x* x* x* ID[31:24] Write Reset x* x* x* x* * Notes: • x = Undefined at reset.
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Chapter 6 System control SYS_UUID6 field descriptions Field 7–0 ID[23:16] Description Universally Unique Identifier 6.6.17 Universally Unique Identifier Register 7 (SYS_UUID7) The read-only SYS_UUIDx registers contain a series of 64-bit number to identify the unique device in the family. Address: 3000h base + FEh offset = 30FEh Bit 7 6 5 4 Read 3 2 1 0 x* x* x* x* ID[15:8] Write Reset x* x* x* x* * Notes: • x = Undefined at reset.
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System Control Registers SYS_UUID8 field descriptions Field 7–0 ID[7:0] Description Universally Unique Identifier MC9S08PA60 Reference Manual, Rev. 1, 9/2012 150 Freescale Semiconductor, Inc.
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Chapter 7 Parallel input/output 7.1 Introduction This device has eight sets of I/O ports, which include up to 57 general-purpose I/O pins. Not all pins are available on all devices. See to determine which functions are available for a specific device. Many of the I/O pins are shared with on-chip peripheral functions, as shown in . The peripheral modules have priority over the I/O, so when a peripheral is enabled, the associated I/O functions are disabled.
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Introduction PTxPEn PTxOEn PTxDn PTxIEn 0 CPU read PTxDn 1 Figure 7-1. Normal I/O structure PTxPEn PTxOEn PTxIEn PTxDn 0 CPU read PTxDn 1 Figure 7-2. SDA(PTA2)/SCL(PTA3) structure MC9S08PA60 Reference Manual, Rev. 1, 9/2012 152 Freescale Semiconductor, Inc.
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Chapter 7 Parallel input/output PTxPEn PTxOEn PTxDn PTxIEn 0 CPU read PTxDn 1 HDRVE Figure 7-3. High drive I/O structure 7.2 Port data and data direction Reading and writing of parallel I/O is accomplished through the port data registers (PTxD). The direction, input or output, is controlled through the input enable or output enable registers. After reset, all parallel I/O default to the Hi-Z state.
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Internal pullup enable When a shared analog function is enabled for a pin, all digital pin functions are disabled. A read of the port data register returns a value of 0 for any bits that have shared analog functions enabled. In general, whenever a pin is shared with both an alternate digital function and an analog function, the analog function has priority such that if both of the digital and analog functions are enabled, the analog function controls the pin.
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Chapter 7 Parallel input/output 7.5 High current drive Output high sink/source current drive can be enabled by setting the corresponding bit in the HDRVE register for PTH1, PTH0, PTE1, PTE0, PTD1, PTD0, PTB5 and PTB4. Output high sink/source current when they are operated as output. High current drive function is disabled if the pin is configured as an input by the parallel I/O control logic.
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Port data registers PORT memory map (continued) Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 30B8 Port A Input Enable Register (PORT_PTAIE) 8 R/W 00h 7.7.18/171 30B9 Port B Input Enable Register (PORT_PTBIE) 8 R/W 00h 7.7.19/172 30BA Port C Input Enable Register (PORT_PTCIE) 8 R/W 00h 7.7.20/173 30BB Port D Input Enable Register (PORT_PTDIE) 8 R/W 00h 7.7.21/175 30BC Port E Input Enable Register (PORT_PTEIE) 8 R/W 00h 7.7.
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Chapter 7 Parallel input/output PORT_PTAD field descriptions (continued) Field Description Reset forces PTAD to all 0s, but these 0s are not driven out of the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 7.7.
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Port data registers PORT_PTCD field descriptions (continued) Field Description Reset forces PTCD to all 0s, but these 0s are not driven out of the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 7.7.
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Chapter 7 Parallel input/output PORT_PTED field descriptions (continued) Field Description Reset forces PTED to all 0s, but these 0s are not driven out of the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 7.7.
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Port data registers PORT_PTGD field descriptions (continued) Field Description For port G pins that are configured as Hi-Z, a read returns uncertainty data. Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level is driven out of the corresponding MCU pin. Reset forces PTGD to all 0s, but these 0s are not driven out of the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups disabled. 7.7.
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Chapter 7 Parallel input/output 7.7.
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Port data registers PORT_HDRVE field descriptions (continued) Field Description 0 1 0 PTB4 PTB5 is disabled to offer high current drive capability. PTB5 is enable to offer high current drive capability. PTB4 This read/write bit enables the high current drive capability of PTB4 0 1 PTB4 is disabled to offer high current drive capability. PTB4 is enable to offer high current drive capability. 7.7.
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Chapter 7 Parallel input/output PORT_PTAOE field descriptions (continued) Field Description 0 1 2 PTAOE2 Output Enable for Port A Bit 2 This read/write bit enables the port A pin as an output. 0 1 1 PTAOE1 Output Disabled for port A bit 2. Output Enabled for port A bit 2. Output Enable for Port A Bit 1 This read/write bit enables the port A pin as an output. 0 1 0 PTAOE0 Output Disabled for port A bit 3. Output Enabled for port A bit 3. Output Disabled for port A bit 1.
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Port data registers PORT_PTBOE field descriptions (continued) Field Description 0 1 4 PTBOE4 Output Enable for Port B Bit 4 This read/write bit enables the port B pin as an output. 0 1 3 PTBOE3 This read/write bit enables the port B pin as an output. This read/write bit enables the port B pin as an output. Output Disabled for port B bit 2. Output Enabled for port B bit 2. Output Enable for Port B Bit 1 This read/write bit enables the port B pin as an output.
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Chapter 7 Parallel input/output PORT_PTCOE field descriptions (continued) Field Description 0 1 6 PTCOE6 Output Enable for Port C Bit 6 This read/write bit enables the port C pin as an output. 0 1 5 PTCOE5 This read/write bit enables the port C pin as an output. This read/write bit enables the port C pin as an output. This read/write bit enables the port C pin as an output. This read/write bit enables the port C pin as an output. Output Disabled for port C bit 2. Output Enabled for port C bit 2.
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Port data registers 7.7.13 Port D Output Enable Register (PORT_PTDOE) Address: 0h base + 30B3h offset = 30B3h Bit Read Write Reset 7 6 5 4 3 2 1 0 PTDOE7 PTDOE6 PTDOE5 PTDOE4 PTDOE3 PTDOE2 PTDOE1 PTDOE0 0 0 0 0 0 0 0 0 PORT_PTDOE field descriptions Field 7 PTDOE7 Description Output Enable for Port D Bit 7 This read/write bit enables the port D pin as an output. 0 1 6 PTDOE6 Output Enable for Port D Bit 6 This read/write bit enables the port D pin as an output.
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Chapter 7 Parallel input/output PORT_PTDOE field descriptions (continued) Field Description 0 1 0 PTDOE0 Output Disabled for port D bit 1. Output Enabled for port D bit 1. Output Enable for Port D Bit 0 This read/write bit enables the port D pin as an output. 0 1 Output Disabled for port D bit 0. Output Enabled for port D bit 0. 7.7.
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Port data registers PORT_PTEOE field descriptions (continued) Field Description 0 1 2 PTEOE2 Output Enable for Port E Bit 2 This read/write bit enables the port E pin as an output. 0 1 1 PTEOE1 Output Disabled for port E bit 2. Output Enabled for port E bit 2. Output Enable for Port E Bit 1 This read/write bit enables the port E pin as an output. 0 1 0 PTEOE0 Output Disabled for port E bit 3. Output Enabled for port E bit 3. Output Disabled for port E bit 1. Output Enabled for port E bit 1.
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Chapter 7 Parallel input/output PORT_PTFOE field descriptions (continued) Field Description 0 1 4 PTFOE4 Output Enable for Port F Bit 4 This read/write bit enables the port F pin as an output. 0 1 3 PTFOE3 This read/write bit enables the port F pin as an output. This read/write bit enables the port F pin as an output. Output Disabled for port F bit 2. Output Enabled for port F bit 2. Output Enable for Port F Bit 1 This read/write bit enables the port F pin as an output.
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Port data registers PORT_PTGOE field descriptions (continued) Field 3 PTGOE3 Description Output Enable for Port G Bit 3 This read/write bit enables the port G pin as an output. 0 1 2 PTGOE2 Output Enable for Port G Bit 2 This read/write bit enables the port G pin as an output. 0 1 1 PTGOE1 Output Disabled for port G bit 2. Output Enabled for port G bit 2. Output Enable for Port G Bit 1 This read/write bit enables the port G pin as an output. 0 1 0 PTGOE0 Output Disabled for port G bit 3.
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Chapter 7 Parallel input/output PORT_PTHOE field descriptions (continued) Field Description 5–3 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 2 PTHOE2 Output Enable for Port H Bit 2 This read/write bit enables the port H pin as an output. 0 1 1 PTHOE1 Output Enable for Port H Bit 1 This read/write bit enables the port H pin as an output. 0 1 0 PTHOE0 Output Disabled for port H bit 2. Output Enabled for port H bit 2. Output Disabled for port H bit 1.
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Port data registers PORT_PTAIE field descriptions (continued) Field Description 0 1 4 Reserved 3 PTAIE3 This field is reserved. This read-only field is reserved and always has the value 0. Input Enable for Port A Bit 3 This read/write bit enables the port A pin as an input. 0 1 2 PTAIE2 This read/write bit enables the port A pin as an input. Input disabled for port A bit 2. Input enabled for port A bit 2. Input Enable for Port A Bit 1 This read/write bit enables the port A pin as an input.
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Chapter 7 Parallel input/output PORT_PTBIE field descriptions (continued) Field Description This read/write bit enables the port B pin as an input. 0 1 5 PTBIE5 Input Enable for Port B Bit 5 This read/write bit enables the port B pin as an input. 0 1 4 PTBIE4 This read/write bit enables the port B pin as an input. This read/write bit enables the port B pin as an input. This read/write bit enables the port B pin as an input. Input disabled for port B bit 2. Input enabled for port B bit 2.
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Port data registers PORT_PTCIE field descriptions Field 7 PTCIE7 Description Input Enable for Port C Bit 7 This read/write bit enables the port C pin as an input. 0 1 6 PTCIE6 Input Enable for Port C Bit 6 This read/write bit enables the port C pin as an input. 0 1 5 PTCIE5 This read/write bit enables the port C pin as an input. This read/write bit enables the port C pin as an input. This read/write bit enables the port C pin as an input. This read/write bit enables the port C pin as an input.
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Chapter 7 Parallel input/output 7.7.21 Port D Input Enable Register (PORT_PTDIE) Address: 0h base + 30BBh offset = 30BBh Bit Read Write Reset 7 6 5 4 3 2 1 0 PTDIE7 PTDIE6 PTDIE5 PTDIE4 PTDIE3 PTDIE2 PTDIE1 PTDIE0 0 0 0 0 0 0 0 0 PORT_PTDIE field descriptions Field 7 PTDIE7 Description Input Enable for Port D Bit 7 This read/write bit enables the port D pin as an input. 0 1 6 PTDIE6 Input Enable for Port D Bit 6 This read/write bit enables the port D pin as an input.
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Port data registers PORT_PTDIE field descriptions (continued) Field Description 0 1 0 PTDIE0 Input disabled for port D bit 1. Input enabled for port D bit 1. Input Enable for Port D Bit 0 This read/write bit enables the port D pin as an input. 0 1 Input disabled for port D bit 0. Input enabled for port D bit 0. 7.7.
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Chapter 7 Parallel input/output PORT_PTEIE field descriptions (continued) Field Description 0 1 2 PTEIE2 Input Enable for Port E Bit 2 This read/write bit enables the port E pin as an input. 0 1 1 PTEIE1 Input disabled for port E bit 2. Input enabled for port E bit 2. Input Enable for Port E Bit 1 This read/write bit enables the port E pin as an input. 0 1 0 PTEIE0 Input disabled for port E bit 3. Input enabled for port E bit 3. Input disabled for port E bit 1. Input enabled for port E bit 1.
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Port data registers PORT_PTFIE field descriptions (continued) Field Description 0 1 4 PTFIE4 Input Enable for Port F Bit 4 This read/write bit enables the port F pin as an input. 0 1 3 PTFIE3 This read/write bit enables the port F pin as an input. This read/write bit enables the port F pin as an input. Input disabled for port F bit 2. Input enabled for port F bit 2. Input Enable for Port F Bit 1 This read/write bit enables the port F pin as an input. 0 1 0 PTFIE0 Input disabled for port F bit 3.
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Chapter 7 Parallel input/output PORT_PTGIE field descriptions (continued) Field 3 PTGIE3 Description Input Enable for Port G Bit 3 This read/write bit enables the port G pin as an input. 0 1 2 PTGIE2 Input Enable for Port G Bit 2 This read/write bit enables the port G pin as an input. 0 1 1 PTGIE1 Input disabled for port G bit 2. Input enabled for port G bit 2. Input Enable for Port G Bit 1 This read/write bit enables the port G pin as an input. 0 1 0 PTGIE0 Input disabled for port G bit 3.
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Port data registers PORT_PTHIE field descriptions (continued) Field 5–3 Reserved 2 PTHIE2 Description This field is reserved. This read-only field is reserved and always has the value 0. Input Enable for Port H Bit 2 This read/write bit enables the port H pin as an input. 0 1 1 PTHIE1 Input Enable for Port H Bit 1 This read/write bit enables the port H pin as an input. 0 1 0 PTHIE0 Input disabled for port H bit 2. Input enabled for port H bit 2. Input disabled for port H bit 1.
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Chapter 7 Parallel input/output PORT_IOFLT0 field descriptions (continued) Field Description 3–2 FLTB Filter selection for input from PTB 1–0 FLTA Filter selection for input from PTA 00 01 10 11 00 01 10 11 BUSCLK FLTDIV1 FLTDIV2 FLTDIV3 BUSCLK FLTDIV1 FLTDIV2 FLTDIV3 7.7.27 Port Filter Register 1 (PORT_IOFLT1) This register sets the filters for input from PTE to PTH.
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Port data registers PORT_IOFLT1 field descriptions (continued) Field 1–0 FLTE Description Filter selection for input from PTE 00 01 10 11 BUSCLK FLTDIV1 FLTDIV2 FLTDIV3 7.7.28 Port Filter Register 2 (PORT_IOFLT2) This register sets the filters for input from RESET AND IRQ. Address: 0h base + 30EEh offset = 30EEh Bit Read Write Reset 7 6 5 0 0 4 3 FLTKBI1 0 0 2 1 FLTKBI0 0 0 0 FLTRST 0 0 0 PORT_IOFLT2 field descriptions Field Description 7–6 Reserved This field is reserved.
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Chapter 7 Parallel input/output 7.7.29 Port Clock Division Register (PORT_FCLKDIV) Configure the high/low level glitch width threshold. Glitches that are shorter than the selected clock width will be filtered out; glitches that are more than twice the selected clock width will not be filtered out (they will pass to the internal circuitry).
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Port data registers 7.7.30 Port A Pullup Enable Register (PORT_PTAPE) Address: 0h base + 30F0h offset = 30F0h Bit Read Write Reset 7 6 5 4 PTAPE7 PTAPE6 PTAPE5 0 0 0 0 0 3 2 1 0 PTAPE3 PTAPE2 PTAPE1 PTAPE0 0 0 0 0 PORT_PTAPE field descriptions Field 7 PTAPE7 Description Pull Enable for Port A Bit 7 This control bit determines if the internal pullup device is enabled for the associated PTA pin. For port A pins that are configured as outputs or Hi-Z, these bits have no effect.
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Chapter 7 Parallel input/output PORT_PTAPE field descriptions (continued) Field Description 0 1 1 PTAPE1 Pull Enable for Port A Bit 1 This control bit determines if the internal pullup device is enabled for the associated PTA pin. For port A pins that are configured as outputs or Hi-Z, these bits have no effect. 0 1 0 PTAPE0 Pullup disabled for port A bit 2. Pullup enabled for port A bit 2. Pullup disabled for port A bit 1. Pullup enabled for port A bit 1.
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Port data registers PORT_PTBPE field descriptions (continued) Field 4 PTBPE4 Description Pull Enable for Port B Bit 4 This control bit determines if the internal pullup device is enabled for the associated PTB pin. For port B pins that are configured as outputs or Hi-Z, these bits have no effect. 0 1 3 PTBPE3 Pull Enable for Port B Bit 3 This control bit determines if the internal pullup device is enabled for the associated PTB pin.
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Chapter 7 Parallel input/output PORT_PTCPE field descriptions (continued) Field Description This control bit determines if the internal pullup device is enabled for the associated PTC pin. For port C pins that are configured as outputs or Hi-Z, these bits have no effect. 0 1 6 PTCPE6 Pull Enable for Port C Bit 6 This control bit determines if the internal pullup device is enabled for the associated PTC pin. For port C pins that are configured as outputs or Hi-Z, these bits have no effect.
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Port data registers PORT_PTCPE field descriptions (continued) Field Description 0 1 Pullup disabled for port C bit 0. Pullup enabled for port C bit 0. 7.7.
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Chapter 7 Parallel input/output PORT_PTDPE field descriptions (continued) Field 2 PTDPE2 Description Pull Enable for Port D Bit 2 This control bit determines if the internal pullup device is enabled for the associated PTD pin. For port D pins that are configured as outputs or Hi-Z, these bits have no effect. 0 1 1 PTDPE1 Pull Enable for Port D Bit 1 This control bit determines if the internal pullup device is enabled for the associated PTD pin.
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Port data registers PORT_PTEPE field descriptions (continued) Field Description This control bit determines if the internal pullup device is enabled for the associated PTE pin. For port E pins that are configured as outputs or Hi-Z, these bits have no effect. 0 1 4 PTEPE4 Pull Enable for Port E Bit 4 This control bit determines if the internal pullup device is enabled for the associated PTE pin. For port E pins that are configured as outputs or Hi-Z, these bits have no effect.
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Chapter 7 Parallel input/output PORT_PTFPE field descriptions Field 7 PTFPE7 Description Pull Enable for Port F Bit 7 This control bit determines if the internal pullup device is enabled for the associated PTF pin. For port F pins that are configured as outputs or Hi-Z, these bits have no effect. 0 1 6 PTFPE6 Pull Enable for Port F Bit 6 This control bit determines if the internal pullup device is enabled for the associated PTF pin.
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Port data registers PORT_PTFPE field descriptions (continued) Field Description This control bit determines if the internal pullup device is enabled for the associated PTF pin. For port F pins that are configured as outputs or Hi-Z, these bits have no effect. 0 1 Pullup disabled for port F bit 0. Pullup enabled for port F bit 0. 7.7.
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Chapter 7 Parallel input/output 7.7.37 Port H Pullup Enable Register (PORT_PTHPE) Address: 0h base + 30F7h offset = 30F7h Bit Read Write Reset 7 6 PTHPE7 PTHPE6 0 0 5 4 3 0 0 0 0 2 1 0 PTHPE2 PTHPE1 PTHPE0 0 0 0 PORT_PTHPE field descriptions Field 7 PTHPE7 Description Pull Enable for Port H Bit 7 This control bit determines if the internal pullup device is enabled for the associated PTH pin. For port H pins that are configured as outputs or Hi-Z, these bits have no effect.
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Port data registers MC9S08PA60 Reference Manual, Rev. 1, 9/2012 194 Freescale Semiconductor, Inc.
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Chapter 8 Clock management 8.1 Clock module This device has ICS, XOSC, and LPO clock modules. The internal clock source (ICS) module provides several clock source options for this device. The module contains a frequency-locked loop (FLL) that is controllable by either an internal or external reference clock. The module can select clock from the FLL or bypass the FLL as a source of the MCU system clock.
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Port A Port B PTB0/KBI0P4/RxD0/ADP4 PTB1/KBI0P5/TxD0/ADP5 PTB2/KBI0P6/SPSCK0/ADP6 PTB3/KBI0P7/MOSI0/ADP7 3 PTB4/FTM2CH4/MISO0 3 PTB5/FTM2CH5/SS0 PTB6/SDA/XTAL PTB7/SCL/EXTAL Port C MODULE (KBI0) PTC0/FTM2CH0/ADP8 PTC1/FTM2CH1/ADP9/ PTC2/FTM2CH2/ADP10 PTC3/FTM2CH3/ADP11 PTC4/FTM1CH0/RTCO PTC5/FTM1CH1 PTC6/RxD1 PTC7/TxD1 Port D BDC PTD0/KBI1P0/FTM2CH2/SPSCK1 3 PTD1/KBI1P1/FTM2CH3/MOSI1 PTD2/KBI1P2/MISO1 PTD3/KBI1P3/SS1 PTD4/KBI1P4 PTD5/KBI1P5 PTD6/KBI1P6/RxD2 PTD7/KBI1P7/TxD2 Port E CPU PTE0/SPSCK0/
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Chapter 8 Clock management 8.2 Internal clock source (ICS) The internal clock source (ICS) module provides clock source options for the MCU. The module contains a frequency-locked loop (FLL) as a clock source that is controllable by an internal or external reference clock. The module can provide this FLL clock or the internal reference clock as a source for the MCU system clock, ICSCLK.
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Internal clock source (ICS) External Reference Clock / Oscillator Internal Clock Source Block ICSIRCLK IRCLKEN IREFSTEN BDIV Internal Reference Clock / 2n n=0-7 ICSOUT LP CLKS FLL SCFTRIMSCTRIM / 2n n=0-7 DCOOUT Filter DCO 2 ICSLCLK ICSBDCCLK CLKSW IREFS BUSCLK RDIV ICSFFCLK IREFST CLKST LOLIE LOLS LOCK CME Figure 8-2. Internal clock source (ICS) 8.2.1.
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Chapter 8 Clock management • Writing a larger value slows down the ICSIRCLK frequency. • Writing a smaller value to the ICSTRM register speeds up the ICSIRCLK frequency. The TRIM bits affect the ICSOUT frequency if the ICS is in FLL engaged internal (FEI), FLL bypassed internal (FBI), or FLL bypassed internal low power (FBILP) mode.
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Internal clock source (ICS) 8.2.1.5 BDC clock The ICS presents the DCO output clock divided by two as ICSLCLK for use as a clock source for BDC communications. ICSLCLK is not available in FLL bypassed internal low power (FBILP) and FLL bypassed external low power (FBELP) modes. The ICSLCLK can be selected as BDC clock. 8.2.2 Modes of operation There are seven modes of operation for the ICS: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop.
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Chapter 8 Clock management The ICS_C1[CLKS] bits can also be changed at anytime, but the actual switch to the newly selected clock is shown by the ICS_S[CLKST] bits. If the newly selected clock is not available, the previous clock remains selected. 8.2.2.
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Internal clock source (ICS) • ICS_C1[CLKS] bits are written to 01 • ICS_C1[IREFS] bit is written to 1 • BDM mode is active or ICS_C2[LP] bit is written to 0 In FLL bypassed internal mode, the ICSOUT clock is derived from the internal reference clock. The FLL clock is controlled by the internal reference clock, and the FLL loop locks the FLL frequency to the 512 times the internal reference frequency. The ICSLCLK will be available for BDC communications, and the internal reference clock is enabled. 8.2.2.
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Chapter 8 Clock management In FLL bypassed external mode, the ICSOUT clock is derived from the external reference clock source. The FLL clock is controlled by the external reference clock, and the FLL loop locks the FLL frequency to the 512 times the external reference frequency, as selected by the ICS_C1[RDIV] bits, so that the ICSLCLK will be available for BDC communications, and the external reference clock is enabled. 8.2.2.
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FLL lock and clock monitor frequency is stable. Timing sensitive operations must wait for the FLL acquisition time, tAquire, before executing. 8.2.3 FLL lock and clock monitor 8.2.3.1 FLL clock lock In FBE and FEE modes, the clock detector source uses the external reference as the reference. When FLL is detected from lock to unlock, the ICS_S[LOLS] bit is set. An interrupt will be generated if ICS_C4[LOLIE] bit is set.
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Chapter 8 Clock management 8.3.1 Initializing FEI mode The following code segment demonstrates setting ICS to FEI mode. Example: 8.3.1.
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Initialization / application information 8.3.4 Initializing FBE mode The following code segment demonstrates setting ICS to FBE mode. Example: 8.3.4.
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Chapter 8 Clock management The external oscillator circuit is designed for use with an external crystal or ceramic resonator to provide an accurate clock source. In its typical configuration, the oscillator is connected in a Pierce oscillator configuration, as shown in the above figure. This figure shows only the logical representation of the internal components and may not represent actual circuitry.
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Initialization / application information MCU XTAL EXTAL RF X1 C1 C2 Figure 8-6. OSC low-power mode connection 8.3.5.3 High-gain configuration In high-gain mode, when ICS_OSCSC[OSCEN] = 1, ICS_OSCSC[OSCOS] = 1, and ICS_OSCSC[HGO] = 1, the series resistor RS must be used. The series resistor RS and feedback resistor RF must be carefully selected to get best performance. The following figure shows the typical OSC high-gain mode connection. MCU EXTAL XTAL RS RF X1 C1 C2 Figure 8-7.
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Chapter 8 Clock management /* the following code segment demonstrates initializing external oscillator */ /* supposing external 32768Hz crystal is installed in low power mode */ ICS_OSCSC = 0xA0; /* low-range, low-power, oscillator required, ERCLK enabled in stop mode */ while (ICS_OSCSC_OSCINIT == 0); /* waiting until oscillator is ready */ 8.4 1 kHz low-power oscillator (LPO) The 1 kHz low-power oscillator acts as a standalone low-frequency clock source in all run, wait, and stop3 modes. 8.
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ICS control registers ICS memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 3038 ICS Control Register 1 (ICS_C1) 8 R/W 04h 8.6.1/210 3039 ICS Control Register 2 (ICS_C2) 8 R/W 20h 8.6.2/211 303A ICS Control Register 3 (ICS_C3) 8 R/W Undefined 8.6.3/212 303B ICS Control Register 4 (ICS_C4) 8 R/W 00h 8.6.4/212 303C ICS Status Register (ICS_S) 8 R 10h 8.6.5/213 303E OSC Status and Control Register (ICS_OSCSC) 8 R/W 00h 8.6.
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Chapter 8 Clock management ICS_C1 field descriptions (continued) Field Description 1. Reset default 2 IREFS Internal Reference Select The IREFS bit selects the reference clock source for the FLL. 0 1 1 IRCLKEN Internal Reference Clock Enable The IRCLKEN bit enables the internal reference clock for use as ICSIRCLK. 0 1 0 IREFSTEN External reference clock selected. Internal reference clock selected. ICSIRCLK inactive. ICSIRCLK active.
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ICS control registers ICS_C2 field descriptions (continued) Field 4 LP Description Low Power Select The LP bit controls whether the FLL is disabled in FLL bypassed modes. 0 1 3–0 Reserved FLL is not disabled in bypass mode. FLL is disabled in bypass modes unless BDM is active. This field is reserved. This read-only field is reserved and always has the value 0. 8.6.
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Chapter 8 Clock management ICS_C4 field descriptions (continued) Field Description 0 1 6 Reserved 5 CME No request on loss of lock. Generate an interrupt request on loss of lock. This field is reserved. This read-only field is reserved and always has the value 0. Clock Monitor Enable Determines if a reset request is made following a loss of external clock indication. The CME bit should be set to a logic 1 only when the ICS is in an operational mode that uses the external clock (FEE or FBE).
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ICS control registers ICS_S field descriptions (continued) Field Description Stop mode entry will also cause the lock status bit to clear and stay cleared until the FLL has reacquired lock. 0 1 5 Reserved 4 IREFST This field is reserved. This read-only field is reserved and always has the value 0. Internal Reference Status The IREFST bit indicates the current source for the reference clock.
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Chapter 8 Clock management ICS_OSCSC field descriptions (continued) Field 5 OSCSTEN Description OSC Enable in Stop mode The OSCSTEN bit controls whether or not the OSC clock remains enabled when MCU enters stop mode. 0 1 4 OSCOS OSC Output Select This bit is used to select the output clock of OSC module. 0 1 3 Reserved 2 RANGE Frequency Range Select Selects the frequency range for the OSC module. Low frequency range of 31.25kHz - 39.0625kHz. High frequency range of 4 - 20MHz.
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System clock gating control registers 8.7.1 System Clock Gating Control 1 Register (SCG_C1) This high page register contains control bits to enable or disable the bus clock to the FTMs, MTIMs, and RTC modules. Gating off the clocks to unused peripherals is used to reduce the MCU's run and wait currents. NOTE User software should disable the peripheral before disabling the clocks to the peripheral.
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Chapter 8 Clock management SCG_C1 field descriptions (continued) Field Description This bit controls the clock gate to the MTIM0 module. 0 1 0 RTC Bus clock to the MTIM0 module is disabled. Bus clock to the MTIM0 module is enabled. RTC Clock Gate Control This bit controls the clock gate to the RTC module. 0 1 Bus clock to the MTRTCIM1 module is disabled. Bus clock to the RTC module is enabled. 8.7.
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System clock gating control registers SCG_C2 field descriptions (continued) Field Description 0 1 3 IPC IPC Clock Gate Control This bit controls the clock gate to the IPC module. 0 1 2 CRC Bus clock to the IPC module is disabled. Bus clock to the IPC module is enabled. CRC Clock Gate Control This bit controls the clock gate to the CRC module. 0 1 1–0 Reserved Bus clock to the NVM module is disabled. Bus clock to the NVM module is enabled. Bus clock to the CRC module is disabled.
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Chapter 8 Clock management SCG_C3 field descriptions (continued) Field Description 0 1 5 SCI1 SCI1 Clock Gate Control This bit controls the clock gate to the SCI1 module. 0 1 4 SCI0 This bit controls the clock gate to the SCI0 module. This bit controls the clock gate to the SPI1 module. This bit controls the clock gate to the SPI0 module. Bus clock to the SPI0 module is disabled. Bus clock to the SPI0 module is enabled. IIC Clock Gate Control This bit controls the clock gate to the IIC module.
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System clock gating control registers Address: 300Ch base + 3h offset = 300Fh Bit Read Write Reset 7 6 ACMP 0 1 0 5 4 ADC 0 1 0 3 1 0 IRQ 0 2 KBI1 KBI0 1 0 1 1 SCG_C4 field descriptions Field 7 ACMP Description ACMP Clock Gate Control This bit controls the clock gate to the ACMP module. 0 1 6 Reserved 5 ADC This field is reserved. This read-only field is reserved and always has the value 0. ADC Clock Gate Control This bit controls the clock gate to the ADC module.
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Chapter 9 Chip configurations 9.1 Introduction This chapter provides details on the individual modules of the device. It includes: • device block diagrams highlighting the specific modules and pin-outs • specific module-to-module interactions not necessarily discussed in the individual module chapters, and • links for more information 9.2 Core modules 9.2.1 Central processor unit (CPU) The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU.
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System modules 9.3 System modules 9.3.1 Watchdog (WDOG) The watchdog timer (WDOG) module triggers a system reset if it is allowed to time out. The program is expected to periodically reload the watchdog timer, thereby preventing it from timing out. However, if a fault occurs that causes the program to stop working, the timer will not be reloaded and it will time out. The resulting trigger of a system reset brings the system back from an unresponsive state into a normal state. 9.
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Port A Port B PTB0/KBI0P4/RxD0/ADP4 PTB1/KBI0P5/TxD0/ADP5 PTB2/KBI0P6/SPSCK0/ADP6 PTB3/KBI0P7/MOSI0/ADP7 3 PTB4/FTM2CH4/MISO0 3 PTB5/FTM2CH5/SS0 PTB6/SDA/XTAL PTB7/SCL/EXTAL Port C MODULE (KBI0) PTC0/FTM2CH0/ADP8 PTC1/FTM2CH1/ADP9/ PTC2/FTM2CH2/ADP10 PTC3/FTM2CH3/ADP11 PTC4/FTM1CH0/RTCO PTC5/FTM1CH1 PTC6/RxD1 PTC7/TxD1 Port D BDC PTD0/KBI1P0/FTM2CH2/SPSCK1 3 PTD1/KBI1P1/FTM2CH3/MOSI1 PTD2/KBI1P2/MISO1 PTD3/KBI1P3/SS1 PTD4/KBI1P4 PTD5/KBI1P5 PTD6/KBI1P6/RxD2 PTD7/KBI1P7/TxD2 Port E CPU PTE0/SPSCK0/
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Memory 9.5 Memory 9.5.1 Random-access-memory (RAM) This device contains4,096 byte static RAM and addresses 0x0040 through 0x103F. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64 KB memory space. 9.5.2 Non-volatile memory (NVM) The NVM is ideal for single-supply applications allowing for field programming without requiring external high voltage sources from program or erase operations.
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Chapter 9 Chip configurations 9.7 Security 9.7.1 Cyclic redundancy check (CRC) The CRC generator module uses a programmable polynomial to generate CRC code for error detection. The 16-bit code is calculated for 8-bit of data at a time, and provides a simple check for all accessible memory locations in flash and RAM. The following figure shows the device block diagram highlighting the CRC module. MC9S08PA60 Reference Manual, Rev. 1, 9/2012 Freescale Semiconductor, Inc.
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Port A Port B PTB0/KBI0P4/RxD0/ADP4 PTB1/KBI0P5/TxD0/ADP5 PTB2/KBI0P6/SPSCK0/ADP6 PTB3/KBI0P7/MOSI0/ADP7 3 PTB4/FTM2CH4/MISO0 3 PTB5/FTM2CH5/SS0 PTB6/SDA/XTAL PTB7/SCL/EXTAL Port C PTC0/FTM2CH0/ADP8 PTC1/FTM2CH1/ADP9/ PTC2/FTM2CH2/ADP10 PTC3/FTM2CH3/ADP11 PTC4/FTM1CH0/RTCO PTC5/FTM1CH1 PTC6/RxD1 PTC7/TxD1 Port D MODULE (KBI0) PTD0/KBI1P0/FTM2CH2/SPSCK1 3 PTD1/KBI1P1/FTM2CH3/MOSI1 PTD2/KBI1P2/MISO1 PTD3/KBI1P3/SS1 PTD4/KBI1P4 PTD5/KBI1P5 PTD6/KBI1P6/RxD2 PTD7/KBI1P7/TxD2 Port E BDC CPU PTE0/SPSCK0/
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Chapter 9 Chip configurations 9.8 Timers 9.8.1 FlexTimer module (FTM) The FlexTimer module is an up to six-channel timer that supports input capture, output compare, and the generation of PWM signals to control electric motor and power management applications. FTM time reference is a 16-bit counter that can be used as an unsigned or signed counter. This MCU contains up to three FTM modules with one 6-channel FTM and two 2channel FTMs.
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Port A Port B PTB0/KBI0P4/RxD0/ADP4 PTB1/KBI0P5/TxD0/ADP5 PTB2/KBI0P6/SPSCK0/ADP6 PTB3/KBI0P7/MOSI0/ADP7 3 PTB4/FTM2CH4/MISO0 3 PTB5/FTM2CH5/SS0 PTB6/SDA/XTAL PTB7/SCL/EXTAL Port C MODULE (KBI0) PTC0/FTM2CH0/ADP8 PTC1/FTM2CH1/ADP9/ PTC2/FTM2CH2/ADP10 PTC3/FTM2CH3/ADP11 PTC4/FTM1CH0/RTCO PTC5/FTM1CH1 PTC6/RxD1 PTC7/TxD1 Port D BDC PTD0/KBI1P0/FTM2CH2/SPSCK1 3 PTD1/KBI1P1/FTM2CH3/MOSI1 PTD2/KBI1P2/MISO1 PTD3/KBI1P3/SS1 PTD4/KBI1P4 PTD5/KBI1P5 PTD6/KBI1P6/RxD2 PTD7/KBI1P7/TxD2 Port E CPU PTE0/SPSCK0/
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Chapter 9 Chip configurations 9.8.1.1 FTM0 interconnection SCI0 TxD signal can be modulated by FTM0 channel 0 PWM output. Please refer to SCI0 TxD modulation. SCI0 RxD signal can be tagged by FTM0 channel 1 input capture function. Please refer to SCI0 RxD filter. 9.8.1.2 FTM1 interconnection ACMP output can be internally connected to FTM1 channel 0 capture input. See ACMP output selection for details. 9.8.1.
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Timers Port A Port B PTB0/KBI0P4/RxD0/ADP4 PTB1/KBI0P5/TxD0/ADP5 PTB2/KBI0P6/SPSCK0/ADP6 PTB3/KBI0P7/MOSI0/ADP7 3 PTB4/FTM2CH4/MISO0 3 PTB5/FTM2CH5/SS0 PTB6/SDA/XTAL PTB7/SCL/EXTAL Port C MODULE (KBI0) PTC0/FTM2CH0/ADP8 PTC1/FTM2CH1/ADP9/ PTC2/FTM2CH2/ADP10 PTC3/FTM2CH3/ADP11 PTC4/FTM1CH0/RTCO PTC5/FTM1CH1 PTC6/RxD1 PTC7/TxD1 Port D BDC PTD0/KBI1P0/FTM2CH2/SPSCK1 3 PTD1/KBI1P1/FTM2CH3/MOSI1 PTD2/KBI1P2/MISO1 PTD3/KBI1P3/SS1 PTD4/KBI1P4 PTD5/KBI1P5 PTD6/KBI1P6/RxD2 PTD7/KBI1P7/TxD2 Port E CPU PTE0
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Chapter 9 Chip configurations 9.8.2.1 MTIM0 as ADC hardware trigger MTIM0 overflow can be used as ADC hardware trigger. See ADC hardware trigger for details. 9.8.3 Real-time counter (RTC) The real-time counter (RTC) consists of one 16-bit counter, one 16-bit comparator, several binary-based and decimal-based prescaler dividers, two clock sources, and one programmable periodic interrupt. This module can be used for time-of-day, calendar or any task scheduling functions.
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Port A Port B PTB0/KBI0P4/RxD0/ADP4 PTB1/KBI0P5/TxD0/ADP5 PTB2/KBI0P6/SPSCK0/ADP6 PTB3/KBI0P7/MOSI0/ADP7 3 PTB4/FTM2CH4/MISO0 3 PTB5/FTM2CH5/SS0 PTB6/SDA/XTAL PTB7/SCL/EXTAL Port C MODULE (KBI0) PTC0/FTM2CH0/ADP8 PTC1/FTM2CH1/ADP9/ PTC2/FTM2CH2/ADP10 PTC3/FTM2CH3/ADP11 PTC4/FTM1CH0/RTCO PTC5/FTM1CH1 PTC6/RxD1 PTC7/TxD1 Port D BDC PTD0/KBI1P0/FTM2CH2/SPSCK1 3 PTD1/KBI1P1/FTM2CH3/MOSI1 PTD2/KBI1P2/MISO1 PTD3/KBI1P3/SS1 PTD4/KBI1P4 PTD5/KBI1P5 PTD6/KBI1P6/RxD2 PTD7/KBI1P7/TxD2 Port E CPU PTE0/SPSCK0/
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Chapter 9 Chip configurations 9.9 Communication interfaces 9.9.1 Serial communications interface (SCI) This device includes three independent serial communications interface (SCI) modules. Typically, these systems are used to connect to the RS232 serial input/output port of a personal computer or workstation. They can also be used to communicate with other embedded controllers. A flexible, 13-bit, modulo-based baud rate generator supports a broad range of standard baud rates beyond 115.2 kBd.
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Port A Port B PTB0/KBI0P4/RxD0/ADP4 PTB1/KBI0P5/TxD0/ADP5 PTB2/KBI0P6/SPSCK0/ADP6 PTB3/KBI0P7/MOSI0/ADP7 3 PTB4/FTM2CH4/MISO0 3 PTB5/FTM2CH5/SS0 PTB6/SDA/XTAL PTB7/SCL/EXTAL Port C MODULE (KBI0) PTC0/FTM2CH0/ADP8 PTC1/FTM2CH1/ADP9/ PTC2/FTM2CH2/ADP10 PTC3/FTM2CH3/ADP11 PTC4/FTM1CH0/RTCO PTC5/FTM1CH1 PTC6/RxD1 PTC7/TxD1 Port D BDC PTD0/KBI1P0/FTM2CH2/SPSCK1 3 PTD1/KBI1P1/FTM2CH3/MOSI1 PTD2/KBI1P2/MISO1 PTD3/KBI1P3/SS1 PTD4/KBI1P4 PTD5/KBI1P5 PTD6/KBI1P6/RxD2 PTD7/KBI1P7/TxD2 Port E CPU PTE0/SPSCK0/
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Chapter 9 Chip configurations 9.9.1.1 SCI0 infrared functions 9.9.1.1.1 SCI0 TxD modulation SCI0 TxD output can be modulated by FTM0 channel 0 PWM output. Please refer to SCI0 TxD modulation. 9.9.1.1.2 SCI0 RxD tag ACMP module output can be directly ejected to SCI0 RxD. In this mode, SCI0 external RxD pinout does not work. Any external signal tagged to ACMP inputs can be set as SCI input. Please refer to SCI0 RxD filter. 9.9.
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Port A Port B PTB0/KBI0P4/RxD0/ADP4 PTB1/KBI0P5/TxD0/ADP5 PTB2/KBI0P6/SPSCK0/ADP6 PTB3/KBI0P7/MOSI0/ADP7 3 PTB4/FTM2CH4/MISO0 3 PTB5/FTM2CH5/SS0 PTB6/SDA/XTAL PTB7/SCL/EXTAL Port C MODULE (KBI0) PTC0/FTM2CH0/ADP8 PTC1/FTM2CH1/ADP9/ PTC2/FTM2CH2/ADP10 PTC3/FTM2CH3/ADP11 PTC4/FTM1CH0/RTCO PTC5/FTM1CH1 PTC6/RxD1 PTC7/TxD1 Port D BDC PTD0/KBI1P0/FTM2CH2/SPSCK1 3 PTD1/KBI1P1/FTM2CH3/MOSI1 PTD2/KBI1P2/MISO1 PTD3/KBI1P3/SS1 PTD4/KBI1P4 PTD5/KBI1P5 PTD6/KBI1P6/RxD2 PTD7/KBI1P7/TxD2 Port E CPU PTE0/SPSCK0/
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Chapter 9 Chip configurations 9.9.3 16-bit serial peripheral interface (16-bit SPI) This device contains a 16-bit serial peripheral interface (SPI1) module which provides for full-duplex, synchronous, serial communication between the MCU and peripheral devices. These peripheral devices can include other microcontrollers, analog-to-digital converters, shift registers, sensors, memories, etc. The following figure shows device block diagram highlighting 16-bit SPI module and pins.
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Port A Port B PTB0/KBI0P4/RxD0/ADP4 PTB1/KBI0P5/TxD0/ADP5 PTB2/KBI0P6/SPSCK0/ADP6 PTB3/KBI0P7/MOSI0/ADP7 3 PTB4/FTM2CH4/MISO0 3 PTB5/FTM2CH5/SS0 PTB6/SDA/XTAL PTB7/SCL/EXTAL Port C MODULE (KBI0) PTC0/FTM2CH0/ADP8 PTC1/FTM2CH1/ADP9/ PTC2/FTM2CH2/ADP10 PTC3/FTM2CH3/ADP11 PTC4/FTM1CH0/RTCO PTC5/FTM1CH1 PTC6/RxD1 PTC7/TxD1 Port D BDC PTD0/KBI1P0/FTM2CH2/SPSCK1 3 PTD1/KBI1P1/FTM2CH3/MOSI1 PTD2/KBI1P2/MISO1 PTD3/KBI1P3/SS1 PTD4/KBI1P4 PTD5/KBI1P5 PTD6/KBI1P6/RxD2 PTD7/KBI1P7/TxD2 Port E CPU PTE0/SPSCK0/
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Chapter 9 Chip configurations 9.9.4 Inter-Integrated Circuit (I2C) This device contains an inter-integrated circuit (I2C) module for communication with other integrated circuits. The following figure shows the device block diagram highlighting I2C module and pins. MC9S08PA60 Reference Manual, Rev. 1, 9/2012 Freescale Semiconductor, Inc.
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Port A Port B PTB0/KBI0P4/RxD0/ADP4 PTB1/KBI0P5/TxD0/ADP5 PTB2/KBI0P6/SPSCK0/ADP6 PTB3/KBI0P7/MOSI0/ADP7 3 PTB4/FTM2CH4/MISO0 3 PTB5/FTM2CH5/SS0 PTB6/SDA/XTAL PTB7/SCL/EXTAL Port C MODULE (KBI0) PTC0/FTM2CH0/ADP8 PTC1/FTM2CH1/ADP9/ PTC2/FTM2CH2/ADP10 PTC3/FTM2CH3/ADP11 PTC4/FTM1CH0/RTCO PTC5/FTM1CH1 PTC6/RxD1 PTC7/TxD1 Port D BDC PTD0/KBI1P0/FTM2CH2/SPSCK1 3 PTD1/KBI1P1/FTM2CH3/MOSI1 PTD2/KBI1P2/MISO1 PTD3/KBI1P3/SS1 PTD4/KBI1P4 PTD5/KBI1P5 PTD6/KBI1P6/RxD2 PTD7/KBI1P7/TxD2 Port E CPU PTE0/SPSCK0/
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Chapter 9 Chip configurations 9.10 Analog 9.10.1 Analog-to-digital converter (ADC) This device contains a 12-bit analog-to-digital converter (ADC), a successive approximation ADC for operation within an integrated microcontroller system-on-chip. The ADC channel assignments, alternate clock function, and hardware trigger function are configured as described following sections. The following figure shows device block diagram highlighting ADC module and pins. MC9S08PA60 Reference Manual, Rev.
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Port A Port B PTB0/KBI0P4/RxD0/ADP4 PTB1/KBI0P5/TxD0/ADP5 PTB2/KBI0P6/SPSCK0/ADP6 PTB3/KBI0P7/MOSI0/ADP7 3 PTB4/FTM2CH4/MISO0 3 PTB5/FTM2CH5/SS0 PTB6/SDA/XTAL PTB7/SCL/EXTAL Port C MODULE (KBI0) PTC0/FTM2CH0/ADP8 PTC1/FTM2CH1/ADP9/ PTC2/FTM2CH2/ADP10 PTC3/FTM2CH3/ADP11 PTC4/FTM1CH0/RTCO PTC5/FTM1CH1 PTC6/RxD1 PTC7/TxD1 Port D BDC PTD0/KBI1P0/FTM2CH2/SPSCK1 3 PTD1/KBI1P1/FTM2CH3/MOSI1 PTD2/KBI1P2/MISO1 PTD3/KBI1P3/SS1 PTD4/KBI1P4 PTD5/KBI1P5 PTD6/KBI1P6/RxD2 PTD7/KBI1P7/TxD2 Port E CPU PTE0/SPSCK0/
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Chapter 9 Chip configurations 9.10.1.1 ADC channel assignments The ADC channel assignments for the device are shown in the following table. Reserved channels convert to an unknown value. 9.10.1.2 Alternate clock The ADC module is capable of performing conversions using the MCU bus clock, the bus clock divided by two, the local asynchronous clock (ADACK) within the module, or the alternate clock, ALTCLK. The alternate clock for the devices is the external oscillator output (OSCOUT).
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Analog • By converting the digital value of the bandgap voltage reference channel using the value of VBG the user can determine VDD. • Convert the temperature sensor channel (AD22) • By using the calculated value of VDD, convert the digital value of AD26 into a voltage, VTEMP The following equation provides an approximate transfer function of the on-chip temperature sensor for VDD = 5.0V, Temp = 25°C, using the ADC at fADCK = 1.0 MHz and configured for long sample.
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Chapter 9 Chip configurations The ACMP features four different inputs muxed with both positive and negative inputs to the ACMP. One is fixed connected to built-in DAC output. ACMP0 and ACMP1 are externally mapped on pinouts. ACMP2 is reserved. When using the bandgap reference voltage as the reference voltage to the built-in DAC, the user must enable the bandgap buffer by setting BGBE =1 in SPMSC1. For value of bandgap voltage reference see Bandgap reference.
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Port A Port B PTB0/KBI0P4/RxD0/ADP4 PTB1/KBI0P5/TxD0/ADP5 PTB2/KBI0P6/SPSCK0/ADP6 PTB3/KBI0P7/MOSI0/ADP7 3 PTB4/FTM2CH4/MISO0 3 PTB5/FTM2CH5/SS0 PTB6/SDA/XTAL PTB7/SCL/EXTAL Port C MODULE (KBI0) PTC0/FTM2CH0/ADP8 PTC1/FTM2CH1/ADP9/ PTC2/FTM2CH2/ADP10 PTC3/FTM2CH3/ADP11 PTC4/FTM1CH0/RTCO PTC5/FTM1CH1 PTC6/RxD1 PTC7/TxD1 Port D BDC PTD0/KBI1P0/FTM2CH2/SPSCK1 3 PTD1/KBI1P1/FTM2CH3/MOSI1 PTD2/KBI1P2/MISO1 PTD3/KBI1P3/SS1 PTD4/KBI1P4 PTD5/KBI1P5 PTD6/KBI1P6/RxD2 PTD7/KBI1P7/TxD2 Port E CPU PTE0/SPSCK0/
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Chapter 9 Chip configurations 9.10.2.1 ACMP configuration information The ACMP features four different inputs muxed with both positive and negative inputs to the ACMP. One is fixed connected to built-in DAC output. ACMP0 and ACMP1 are externally mapped on pinouts. ACMP2 is reserved. The following table shows the connection of ACMP input assignments. Table 9-2.
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Human-machine interfaces HMI 9.11 Human-machine interfaces HMI 9.11.1 Keyboard interrupts (KBI) This device has two KBI modules with up to 16 keyboard interrupt inputs grouped in two KBI modules available depending on packages. The following figure shows the device block diagram with the KBI modules and pins highlighted. MC9S08PA60 Reference Manual, Rev. 1, 9/2012 248 Freescale Semiconductor, Inc.
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Port A Port B PTB0/KBI0P4/RxD0/ADP4 PTB1/KBI0P5/TxD0/ADP5 PTB2/KBI0P6/SPSCK0/ADP6 PTB3/KBI0P7/MOSI0/ADP7 3 PTB4/FTM2CH4/MISO0 3 PTB5/FTM2CH5/SS0 PTB6/SDA/XTAL PTB7/SCL/EXTAL Port C MODULE (KBI0) PTC0/FTM2CH0/ADP8 PTC1/FTM2CH1/ADP9/ PTC2/FTM2CH2/ADP10 PTC3/FTM2CH3/ADP11 PTC4/FTM1CH0/RTCO PTC5/FTM1CH1 PTC6/RxD1 PTC7/TxD1 Port D BDC PTD0/KBI1P0/FTM2CH2/SPSCK1 3 PTD1/KBI1P1/FTM2CH3/MOSI1 PTD2/KBI1P2/MISO1 PTD3/KBI1P3/SS1 PTD4/KBI1P4 PTD5/KBI1P5 PTD6/KBI1P6/RxD2 PTD7/KBI1P7/TxD2 Port E CPU PTE0/SPSCK0/
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Human-machine interfaces HMI MC9S08PA60 Reference Manual, Rev. 1, 9/2012 250 Freescale Semiconductor, Inc.
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Chapter 10 Central processor unit 10.1 Introduction This section provides summary information about the registers, addressing modes, special operations, instructions and exceptions processing of the HCS08 V6 CPU. The HCS08 V6 CPU is fully source- and object-code-compatible with the HCS08 CPU. 10.1.
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Programmer's Model and CPU Registers • Indexed relative to H:X — Five submodes including auto increment • Indexed relative to SP — Improves C efficiency dramatically • Memory-to-memory data move instructions with four address mode combinations • Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (BCD) operations • Efficient bit manipulation instructions • STOP and WAIT instructions to invoke low-power op
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Chapter 10 Central processor unit accumulator can be loaded from memory using various addressing modes to specify the address where the loaded data comes from, or the contents of A can be stored to memory using various addressing modes to specify the address where data from A will be stored. Reset has no effect on the contents of the A accumulator. 10.2.
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Programmer's Model and CPU Registers 10.2.4 Program Counter (PC) The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. During normal program execution, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, interrupt, and return operations load the program counter with an address other than that of the next sequential location.
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Chapter 10 Central processor unit Table 10-1. CCR Register Field Descriptions (continued) Field 3 I Description Interrupt Mask Bit — When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the first instruction of the interrupt service routine is executed.
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Addressing Modes Every addressing mode, except inherent, generates a 16-bit effective address. The effective address is the address of the memory location that the instruction acts on. Effective address computations do not require extra execution cycles. The HCS08 V6 CPU uses the 16 addressing modes described in the following sections. 10.3.1 Inherent Addressing Mode (INH) In this addressing mode, instructions either have no operands or all operands are in internal CPU registers.
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Chapter 10 Central processor unit Example: LDA CPHX LDHX #$55 #$FFFF #$67 The size of the immediate operand is implied by the instruction context. In the third example, the instruction implies a 16-bit immediate value, but only an 8-bit value is supplied. In this case the assembler generates the 16-bit value $0067 because the CPU expects a 16-bit value in the instruction stream. 10.3.
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Addressing Modes 10.3.5 Extended Addressing Mode (EXT) In extended addressing, the full 16-bit address of the memory location to be operated on is provided in the instruction. Extended addressing can access any location in the 64 KB memory map. Example: LDA $F03B This instruction uses extended addressing because $F03B is above the zero page. In most assemblers, the programmer does not need to specify whether an instruction is direct or extended.
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Chapter 10 Central processor unit 10.3.6.3 Indexed, 8-Bit Offset (IX1) Indexed with 8-bit offset instructions are two-byte instructions that can access data with a variable address. The CPU adds the unsigned bytes in the H:X register to the unsigned byte immediately following the opcode. The sum is the effective address. Indexed, 8-bit offset instructions are useful in selecting the k-th element in an n-element table. The table can begin anywhere and can extend as far as the address map allows.
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Addressing Modes 10.3.6.6 SP-Relative, 8-Bit Offset (SP1) Stack pointer, 8-bit offset instructions are three-byte instructions that address operands in much the same way as indexed 8-bit offset instructions, except that the 8-bit offset is added to the value of the stack pointer instead of the index register. The stack pointer, 8-bit offset addressing mode permits easy addressing of data on the stack.
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Chapter 10 Central processor unit 10.3.7.2 Immediate to Direct This addressing mode is used to move an 8-bit constant to any location in the direct page memory. The source data is the byte immediately following the opcode, and the destination is addressed by the second byte following the opcode. 10.3.7.
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Operation modes remain active when the MCU enters stop mode. In this case, if a serial BACKGROUND command is issued to the MCU through the background debug interface while the CPU is in stop mode, CPU clocks will resume and the CPU will enter active background mode where other serial background commands can be processed. This ensures that a host development system can still gain access to a target MCU even if it is in stop mode. 10.4.
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Chapter 10 Central processor unit The active background mode functions are managed through the background debug controller (BDC) in the HCS08 V6 core. The BDC provides the means for analyzing MCU operation during software development. Active background mode is entered in any of the following ways: • When the BKGD/MS pin is low at the time the MCU exits reset. • When a BACKGROUND command is received through the BKGD pin. • When a BGND instruction is executed. • When encountering a BDC breakpoint.
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Operation modes 10.4.4 Security mode Usually HCS08 V6 MCUs are implemented with a secure operating mode. When in secure mode, external access to internal memory is restricted, so that only instructions fetched from secure memory can access secure memory. The method by which the MCU is put into secure mode is not defined by the HCS08 V6 Core. The core receives an external input signal that, when asserted, informs to the core that the MCU is in secure mode.
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Chapter 10 Central processor unit Table 10-2. Security conditions for read access (continued) Inputs conditions Read control Security enabled Ram, flash or EEPROM access Program or vector read Current CPU instruction from secure memory Current access is via BDC Read access allowed 1 1 0 1 0 1 1 1 0 1 1 0 1 1 0 0 0 0 1 1 0 0 1 0 10.5 HCS08 V6 Opcodes The HCS08 V6 Core has 254 one-byte opcodes and 47 two-byte opcodes, totaling 301 opcodes.
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Special Operations 10.6.2 Interrupt Sequence When an interrupt is requested, the CPU completes the current instruction before responding to the interrupt. At this point, the program counter is pointing at the start of the next instruction, which is where the CPU should return after servicing the interrupt.
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Chapter 10 Central processor unit 10.7 Instruction Set Summary Table 10-3.
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Instruction Set Summary Table 10-3.
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Chapter 10 Central processor unit Table 10-3.
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Instruction Set Summary Table 10-3.
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Chapter 10 Central processor unit Operation Description V H I N Z C Address Mode Bus Cycles Source Form Opcode Effect on CCR Operand Table 10-3.
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Instruction Set Summary Table 10-3.
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Chapter 10 Central processor unit Table 10-3.
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Instruction Set Summary Table 10-3.
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Chapter 10 Central processor unit Bus Cycles V H I N Z C Address Mode Opcode Effect on CCR Operand Table 10-3.
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Instruction Set Summary Table 10-3.
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Chapter 10 Central processor unit Table 10-3.
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Instruction Set Summary MC9S08PA60 Reference Manual, Rev. 1, 9/2012 278 Freescale Semiconductor, Inc.
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Chapter 11 Keyboard Interrupts (KBI) 11.1 Introduction 11.1.1 Features The KBI features include: • Up to eight keyboard interrupt pins with individual pin enable bits • Each keyboard interrupt pin is programmable as: • falling edge sensitivity only • rising edge sensitivity only • both falling edge and low-level sensitivity • both rising edge and high-level sensitivity • One software-enabled keyboard interrupt • Exit from low-power modes 11.1.
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Introduction 11.1.2.1 KBI in Wait Mode Executing the Wait instruction places the MCU into wait mode. The KBI interrupt should be enabled (KBI_SC[KBIE] = 1), if desired, before executing the Wait instruction, allowing the KBI to continue to operate while the MCU is in wait mode. An enabled KBI pin (KBPEx = 1) can be used to bring the MCU out of wait mode if the KBI interrupt is enabled (KBI_SC[KBIE] = 1). 11.1.2.
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Chapter 11 Keyboard Interrupts (KBI) 11.2 External Signals Description The KBI input pins can be used to detect either falling edges, or both falling edge and low-level interrupt requests. The KBI input pins can also be used to detect either rising edges, or both rising edge and high-level interrupt requests. The signal properties of KBI are shown in the following table: Table 11-1. External signals description Signal KBIxPn Function I/O Keyboard interrupt pins I 11.
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Memory Map and Registers 11.4.1 KBI Status and Control Register (KBIx_SC) KBI_SC contains the status flag and control bits, which are used to configure the KBI. Address: Base address + 0h offset Bit 7 6 Read 5 4 3 0 Write Reset 2 KBF KBACK 0 0 0 0 0 0 1 0 KBIE KBMOD 0 0 KBIx_SC field descriptions Field 7–4 Reserved 3 KBF Description This field is reserved. This read-only field is reserved and always has the value 0.
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Chapter 11 Keyboard Interrupts (KBI) KBIx_PE field descriptions Field 7–0 KBIPE Description KBI Pin Enables Each of the KBIPEn bits enable the corresponding KBI interrupt pin. 0 1 Pin is not enabled as KBI interrupt. Pin is enabled as KBI interrupt. 11.4.3 KBIx Edge Select Register (KBIx_ES) KBIx_ES contains the edge select control bits.
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Functional Description 11.5.1 Edge-Only Sensitivity Synchronous logic is used to detect edges. A falling edge is detected when an enabled keyboard interrupt (KBIPEn=1) input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising edge is detected when the input signal is seen as a logic 0 (the deasserted level) during one bus cycle and then a logic 1 (the asserted level) during the next cycle.
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Chapter 11 Keyboard Interrupts (KBI) 11.5.4 KBI Initialization When a keyboard interrupt pin is first enabled, it is possible to get a false keyboard interrupt flag. To prevent a false interrupt request during keyboard initialization, the user should do the following: 1. 2. 3. 4. 5. 6. Mask keyboard interrupts by clearing KBIx_SC[KBIE]. Enable the KBI polarity by setting the appropriate KBIx_ES[KBEDGn] bits. Before using internal pullup resistors, configure the associated bits in PORT_PTxPE.
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Functional Description MC9S08PA60 Reference Manual, Rev. 1, 9/2012 286 Freescale Semiconductor, Inc.
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Chapter 12 FlexTimer Module (FTM) 12.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The FlexTimer module is a two to eight channel timer which supports input capture, output compare, and the generation of PWM signals to control electric motor and power management applications. The FTM time reference is a 16-bit counter that can be used as an unsigned or signed counter. 12.1.
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Introduction Motor control and power conversion features have been added through a dedicated set of registers. The new features, such as hardware dead time insertion, polarity, fault control, and masking, greatly reduce loading on the execution software and are usually each controlled by a group of registers. All of the new features are disabled after reset by default.
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Chapter 12 FlexTimer Module (FTM) • In output compare mode the output signal can be set, cleared, or toggled on match • All channels can be configured for center-aligned PWM mode • Each pair of channels can be combined to generate a PWM signal with independent control of both edges of PWM signal • The FTM channels can operate as pairs with equal outputs, pairs with complementary outputs, or independent channels with independent outputs • The deadtime insertion is available for each complementary pair • Gen
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Introduction 12.1.4 Block diagram The FTM uses one input/output (I/O) pin per channel, CHn (FTM channel (n)) where n is the channel number (0–7). The following figure shows the FTM structure. The central component of the FTM is the 16-bit counter with programmable initial and final values and its counting can be up or up-down. MC9S08PA60 Reference Manual, Rev. 1, 9/2012 290 Freescale Semiconductor, Inc.
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Chapter 12 FlexTimer Module (FTM) CLKS[1:0] FTMEN no clock selected (FTM counter disable) PS[2:0] system clock divided by 2 fixed frequency clock Prescaler 3( 1, 2, 4, 8, 16, 32, 64 or 128) synchronizer external clock INITTRIGEN CPWMS initialization trigger CNTINH:L CAPTEST TOIE FTM counter (16-bit counter) FAULTM[1:0] FFVAL[3:0] FAULTIE FAULTnEN* FFLTRnEN* fault input n* MODH:L FAULTIN FAULTF FAULTFn* Fault control fault interrupt channel 0 input Input capture mode logic C0VH:L C1VH:L
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Signal description 12.2 Signal description The following table shows the user-accessible signals for the FTM. Table 12-1. Signal properties Name EXTCLK Function External clock – FTM external clock can be selected to drive the FTM counter. CHn1 Channel (n) – I/O pin associated with FTM channel (n). FAULTj2 Fault input (j) – input pin associated with fault input (j). 1. n = channel number (0 to 7) 2. j = fault input (0 to 3) 12.2.
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Chapter 12 FlexTimer Module (FTM) 12.3 Memory map and register definition This section provides a detailed description of all FTM registers. 12.3.1 Module memory map This section presents a high-level summary of the FTM registers and how they are mapped. The FTM memory map can be split into two sets of registers. The first set has the original TPM registers. Starting with Counter Initial Value High (CNTINH), the second set has the FTM specific registers.
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Memory map and register definition FTM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 2A Channel Value Low (FTM0_C1VL) 8 R/W 00h 12.3.10/304 2B Channel Status and Control (FTM0_C2SC) 8 R/W 00h 12.3.8/300 2C Channel Value High (FTM0_C2VH) 8 R/W 00h 12.3.9/303 2D Channel Value Low (FTM0_C2VL) 8 R/W 00h 12.3.10/304 2E Channel Status and Control (FTM0_C3SC) 8 R/W 00h 12.3.
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Chapter 12 FlexTimer Module (FTM) FTM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 37 Channel Value Low (FTM1_C0VL) 8 R/W 00h 12.3.10/304 38 Channel Status and Control (FTM1_C1SC) 8 R/W 00h 12.3.8/300 39 Channel Value High (FTM1_C1VH) 8 R/W 00h 12.3.9/303 3A Channel Value Low (FTM1_C1VL) 8 R/W 00h 12.3.10/304 3B Channel Status and Control (FTM1_C2SC) 8 R/W 00h 12.3.
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Memory map and register definition FTM memory map (continued) Absolute address (hex) Register name Width Access (in bits) Reset value Section/ page 30C4 Modulo Low (FTM2_MODL) 8 R/W 00h 12.3.7/300 30C5 Channel Status and Control (FTM2_C0SC) 8 R/W 00h 12.3.8/300 30C6 Channel Value High (FTM2_C0VH) 8 R/W 00h 12.3.9/303 30C7 Channel Value Low (FTM2_C0VL) 8 R/W 00h 12.3.10/304 30C8 Channel Status and Control (FTM2_C1SC) 8 R/W 00h 12.3.
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Chapter 12 FlexTimer Module (FTM) 12.3.3 Status and Control (FTMx_SC) SC contains the overflow status flag and control bits used to configure the interrupt enable, FTM configuration, clock source, and prescaler factor. These controls relate to all channels within this module.
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Memory map and register definition FTMx_SC field descriptions (continued) Field 2–0 PS Description Prescale Factor Selection Selects one of 8 division factors for the clock source selected by CLKS. The new prescaler factor affects the clock source on the next system clock cycle after the new value is updated into the register bits. PS is write protected. It can be written only when MODE[WPDIS] = 1.
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Chapter 12 FlexTimer Module (FTM) FTMx_CNTH field descriptions Field 7–0 COUNT_H Description Counter value high byte 12.3.5 Counter Low (FTMx_CNTL) See the description for the Counter High register. Address: Base address + 2h offset Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 COUNT_L 0 0 0 0 FTMx_CNTL field descriptions Field 7–0 COUNT_L Description Counter value low byte 12.3.
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Memory map and register definition It is recommended to initialize the FTM counter, by writing to CNTH or CNTL, before writing to the FTM modulo register to avoid confusion about when the first counter overflow will occur. Address: Base address + 3h offset Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 3 2 1 0 0 0 0 0 MOD_H 0 0 0 0 FTMx_MODH field descriptions Field 7–0 MOD_H Description High byte of the modulo value 12.3.
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Chapter 12 FlexTimer Module (FTM) Table 12-70.
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Memory map and register definition Table 12-71.
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Chapter 12 FlexTimer Module (FTM) FTMx_CnSC field descriptions (continued) Field Description The functionality of ELSB and ELSA depends on the channel mode. See the table in the register description. ELSA is write protected. It can be written only when MODE[WPDIS] = 1. 1 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 0 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 12.3.
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Memory map and register definition output modes operation after normal execution resumes. Writes to the channel value registers while BDM is active do not interfere with the partial completion of a coherency sequence. After the write coherency mechanism has been fully exercised, the channel value registers are updated using the buffered values while BDM was not active.
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Chapter 12 FlexTimer Module (FTM) When BDM is active, the write coherency mechanism is frozen such that the buffer latches remain in the state they were in when the BDM became active, even if one or both bytes of the counter initial value register are written while BDM is active. Any write to the counter initial value registers bypasses the buffer latches and writes directly to the counter initial value register while BDM is active.
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Memory map and register definition Each CHnF bit in STATUS is a mirror of CHnF bit in CnSC. All CHnF bits can be checked using only one read of STATUS. All CHnF bits can be cleared by reading STATUS followed by writing 0x00 to STATUS. Hardware sets the individual channel flags when an event occurs on the channel. CHF is cleared by reading STATUS while CHnF is set and then writing a 0 to the CHF bit. Writing a 1 to CHF has no effect.
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Chapter 12 FlexTimer Module (FTM) FTMx_STATUS field descriptions (continued) Field Description 0 1 3 CH3F Channel 3 Flag See the register description. 0 1 2 CH2F See the register description. No channel event has occurred. A channel event has occurred. Channel 1 Flag See the register description. 0 1 0 CH0F No channel event has occurred. A channel event has occurred. Channel 2 Flag 0 1 1 CH1F No channel event has occurred. A channel event has occurred. No channel event has occurred.
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Memory map and register definition FTMx_MODE field descriptions (continued) Field Description 0 1 6–5 FAULTM Fault control interrupt is disabled. Fault control interrupt is enabled. Fault Control Mode Defines the FTM fault control mode. FAULTM is write protected. These bits can be written only if MODE[WPDIS] = 1. 00 01 10 11 4 CAPTEST Capture Test Mode Enable Enables the capture test mode. CAPTEST bit is write protected. This bit can be written only if WPDIS = 1.
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Chapter 12 FlexTimer Module (FTM) 12.3.15 Synchronization (FTMx_SYNC) This register configures the PWM synchronization. A synchronization event can perform the synchronized update of MOD, CV, and OUTMASK registers with the value of their write buffer and the FTM counter initialization. NOTE The software trigger (SWSYNC bit) and hardware triggers (TRIG0, TRIG1, and TRIG2 bits) have a potential conflict if used together.
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Memory map and register definition FTMx_SYNC field descriptions (continued) Field Description 0 1 5 TRIG1 PWM Synchronization External Trigger 1 Selects external trigger 1 as the PWM synchronization trigger. External trigger 1 occurs when the FTM detects a rising edge in the trigger 1 input signal. 0 1 4 TRIG0 Selects external trigger 0 as the PWM synchronization trigger. External trigger 0 occurs when the FTM detects a rising edge in the trigger 0 input signal.
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Chapter 12 FlexTimer Module (FTM) 12.3.16 Initial State for Channel Output (FTMx_OUTINIT) Address: Base address + 1Ch offset Bit Read Write Reset 7 6 5 4 3 2 1 0 CH7OI CH6OI CH5OI CH4OI CH3OI CH2OI CH1OI CH0OI 0 0 0 0 0 0 0 0 FTMx_OUTINIT field descriptions Field 7 CH7OI Description Channel 7 Output Initialization Value Selects the value that is forced into the channel output when the initialization occurs.
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Memory map and register definition FTMx_OUTINIT field descriptions (continued) Field Description 0 1 0 CH0OI The initialization value is 0. The initialization value is 1. Channel 0 Output Initialization Value Selects the value that is forced into the channel output when the initialization occurs. 0 1 The initialization value is 0. The initialization value is 1. 12.3.17 Output Mask (FTMx_OUTMASK) This register provides a mask for each FTM channel.
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Chapter 12 FlexTimer Module (FTM) FTMx_OUTMASK field descriptions (continued) Field Description 0 1 4 CH4OM Channel 4 Output Mask Defines if the channel output is masked (forced to its inactive state) or unmasked (it continues to operate normally). 0 1 3 CH3OM Defines if the channel output is masked (forced to its inactive state) or unmasked (it continues to operate normally). Defines if the channel output is masked (forced to its inactive state) or unmasked (it continues to operate normally).
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Memory map and register definition NOTE The channel (n) is the even channel and the channel (n+1) is the odd channel of a pair of channels. Address: Base address + 1Eh offset + (1d × i), where i=0d to 2d Bit 7 6 5 4 3 2 1 0 Read Write Reset 0 FAULTEN SYNCEN DTEN DECAP DECAPEN COMP COMBINE 0 0 0 0 0 0 0 0 FTMx_COMBINEn field descriptions Field Description 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0.
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Chapter 12 FlexTimer Module (FTM) FTMx_COMBINEn field descriptions (continued) Field Description DECAPEN is write protected, this bit can be written only if MODE[WPDIS] = 1. 0 1 1 COMP The dual edge capture mode in this pair of channels is disabled. The dual edge capture mode in this pair of channels is enabled. Complement of Channel (n) Enables complementary mode for the combined channels. In complementary mode the channel (n+1) output is the inverse of the channel (n) output.
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Memory map and register definition FTMx_DEADTIME field descriptions (continued) Field Description DTVAL selects the number of deadtime counts inserted as follows: • When DTVAL is 0, no counts are inserted. • When DTVAL is 1, 1 count is inserted. • When DTVAL is 2, 2 counts are inserted. This pattern continues up to a possible 63 counts. DTVAL is write protected. It can be written only when MODE[WPDIS] = 1. 12.3.
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Chapter 12 FlexTimer Module (FTM) FTMx_EXTTRIG field descriptions (continued) Field 4 CH0TRIG Description Channel 0 Trigger Enable Enables the generation of the channel trigger when the FTM counter is equal to the CV register. 0 1 3 CH5TRIG Channel 5 Trigger Enable Enables the generation of the channel trigger when the FTM counter is equal to the CV register. 0 1 2 CH4TRIG Enables the generation of the channel trigger when the FTM counter is equal to the CV register.
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Memory map and register definition FTMx_POL field descriptions Field 7 POL7 Description Channel 7 Polarity Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 6 POL6 The channel polarity is active high. The channel polarity is active low. Channel 6 Polarity Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 5 POL5 The channel polarity is active high.
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Chapter 12 FlexTimer Module (FTM) FTMx_POL field descriptions (continued) Field 0 POL0 Description Channel 0 Polarity Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 The channel polarity is active high. The channel polarity is active low. 12.3.22 Fault Mode Status (FTMx_FMS) This register contains the fault detection flags, write protection enable bit, and the logic OR of the enable fault inputs.
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Memory map and register definition FTMx_FMS field descriptions (continued) Field Description 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 3 FAULTF3 Fault Detection Flag 3 Set by hardware when fault control is enabled, the corresponding fault input is enabled and a fault condition is detected in the fault input.
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Chapter 12 FlexTimer Module (FTM) FTMx_FMS field descriptions (continued) Field Description If another fault condition is detected at fault input n before the clearing sequence is completed, the sequence is reset so FAULTFn remains set after the clearing sequence is completed for the earlier fault condition. 0 1 No fault condition was detected in the fault input. A fault condition was detected in the fault input. 12.3.
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Memory map and register definition 12.3.24 Fault Input Filter Control (FTMx_FLTFILTER) This register selects the fault inputs and enables the fault input filter. Address: Base address + 28h offset Bit Read Write Reset 7 6 5 4 3 2 0 0 1 0 0 0 FFVAL 0 0 0 0 0 FTMx_FLTFILTER field descriptions Field 7–4 Reserved 3–0 FFVAL Description This field is reserved. This read-only field is reserved and always has the value 0. Fault Input Filter Selects the filter value for the fault inputs.
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Chapter 12 FlexTimer Module (FTM) FTMx_FLTCTRL field descriptions (continued) Field 6 FFLTR2EN Description Fault Input 2 Filter Enable Enables the filter for the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. 0 1 5 FFLTR1EN Fault input filter is disabled. Fault input filter is enabled. Fault Input 1 Filter Enable Enables the filter for the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1.
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Functional Description 12.4 Functional Description The following sections describe the FTM features. The notation used in this document to represent the counters and the generation of the signals is shown in the following figure.
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Chapter 12 FlexTimer Module (FTM) The fixed frequency clock is an alternative clock source for the FTM counter that allows the selection of a clock other than the system clock or an external clock. This clock input is defined by chip integration. Refer to chip specific documentation for further information. Due to FTM hardware implementation limitations, the frequency of the fixed frequency clock must not exceed the system clock frequency.
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Functional Description 12.4.3.1 Up counting Up counting is selected when (CPWMS = 0). CNTINH:L defines the starting value of the count and MODH:L defines the final value of the count; see the following figure. The value of CNTINH:L is loaded into the FTM counter, and the counter increments until the value of MODH:L is reached, at which point the counter is reloaded with CNTINH:L. The FTM period when using up counting is (MODH:L – CNTINH:L + 0x0001) × period of the FTM counter clock.
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Chapter 12 FlexTimer Module (FTM) FTM counting is up CNTINH:L = 0x0000 MODH:L = 0x0004 FTM counter 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2 TOF bit set TOF bit set TOF bit set TOF bit period of FTM counter clock period of counting = (MODH:L - CNTINH:L + 0x0001) x period of FTM counter clock = (MODH:L + 0x0001) x period of FTM counter clock Figure 12-189.
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Functional Description FTM counting is up MODH:L = 0x0005 CNTINH:L = 0x0015 load of CNTINH:L FTM counter load of CNTINH:L 0x0005 0x0015 0x0016 ... 0xFFFE 0xFFFF 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0015 0x0016 ... TOF bit set TOF bit set TOF bit Figure 12-190. Example of up counting when the value of CNTIN registers is greater than the value of MOD registers 12.4.3.2 Up-down counting Up-down counting is selected when (CPWMS = 1).
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Chapter 12 FlexTimer Module (FTM) FTM counting is up-down CNTINH:L = 0x0000 MODH:L = 0x0004 FTM counter 0 1 2 3 4 3 2 1 0 1 2 3 4 3 2 1 0 1 2 3 4 TOF bit set TOF bit period of FTM counter clock set TOF bit period of counting = 2 x (MODH:L - CNTINH:L) x period of FTM counter clock = 2 x MODH:L x period of FTM counter clock Figure 12-191. Example of up-down counting when CNTIN = 0x0000 Note • The up-down counting is available only when (CNTINH:L = 0x0000).
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Functional Description • (CPWMS = 0) • (CNTINH:L = 0x0000) • (MODH:L = 0xFFFF) In this case, the FTM counter runs free from 0x0000 through 0xFFFF and the TOF bit is set when the FTM counter changes from 0xFFFF to 0x0000. 12.4.3.4 Counter reset Any write to CNTH or CNTL register resets the FTM counter to the value of CNTINH:L and the channels output to its initial value, except for channels in output compare mode.
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Chapter 12 FlexTimer Module (FTM) was rising edge selected? is filter enabled? 0 synchronizer 0 channel (n) input system clock D Q CLK D CHnIE Filter* 1 channel (n) interrupt CHnF 1 edge detector Q CLK rising edge 0 CnVH:L[15:0] falling edge 0 1 0 was falling edge selected? * NOTE: Filtering function is only available in the inputs of channel 0, 1, 2, and 3 FTM counter Figure 12-193.
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Functional Description CHnFVAL[3:0] Logic to control channel (n) input after the synchronizer the filter counter 5-bit up counter divided by 4 Logic to define the filter output S filter output Q C CLK system clock Figure 12-194. Channel input filter If the opposite edge appears on the input signal before validation, the counter is reset. At the next input transition, the counter starts counting again.
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Chapter 12 FlexTimer Module (FTM) In output compare mode, the FTM can generate timed pulses with programmable position, polarity, duration, and frequency. When the counter matches the value in the CnVH:CnVL registers of an output compare channel, the channel (n) output can be set, cleared, or toggled. When a channel is initially configured to toggle mode, the previous value of the channel output is held until the first output compare event occurs.
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Functional Description It is possible to use the output compare mode with (ELSnB:ELSnA = 0:0). In this case, when the counter reaches the value in the CnVH:CnVL registers, the CHnF bit is set and the channel (n) interrupt is generated, if CHnIE = 1. However, the channel (n) output is not modified and controlled by FTM. Note • Output compare mode is available only with (CNTINH:CNTINL = 0x0000). • Output compare mode with (CNTINH:CNTINL ≠ 0x0000) is not recommended and its results are not guaranteed. 12.4.
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Chapter 12 FlexTimer Module (FTM) If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced high at the counter overflow, when the value of CNTINH:L is loaded into the FTM counter. Additionally, it is forced low at the channel (n) match, when the FTM counter = CnVH:L. See the following figure. MODH:L = 0x0008 CnVH:L = 0x0005 counter overflow CNTH:L ... 0 channel (n) match 1 2 3 4 5 counter overflow 6 7 8 0 1 2 ... channel (n) output previous value CHnF bit TOF bit Figure 12-200.
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Functional Description 12.4.7 Center-aligned PWM (CPWM) mode The center-aligned mode is selected when all of the following apply: • (DECAPEN = 0) • (COMBINE = 0) • (CPWMS = 1) The CPWM pulse width (duty cycle) is determined by 2 × (CnVH:L – CNTINH:L). The period is determined by 2 × (MODH:L – CNTINH:L). See the following figure. MODH:L must be kept in the range of 0x0001 to 0x7FFF because values outside this range can produce ambiguous results.
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Chapter 12 FlexTimer Module (FTM) counter overflow channel (n) match in down counting MODH:L = 0x0008 CnVH:L = 0x0005 ... CNTH:L 7 8 7 6 5 4 3 counter overflow channel (n) match in down counting channel (n) match in up counting 2 1 0 1 2 3 4 5 6 7 8 7 6 5 ... channel (n) output previous value CHnF bit TOF bit Figure 12-203.
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Functional Description 12.4.8 Combine mode The combine mode is selected when all of the following apply: • (FTMEN = 1) • (DECAPEN = 0) • (COMBINE = 1) • (CPWMS = 0) In combine mode, the even channel (n) and adjacent odd channel (n+1) are combined to generate a PWM signal in the channel (n) output. In the combine mode, the PWM period is determined by (MODH:L – CNTINH:L + 0x0001) and the PWM pulse width (duty cycle) is determined by (|C(n+1)VH:L – C(n)VH:L|).
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Chapter 12 FlexTimer Module (FTM) FTM counter MODH:L C(n+1)VH:L C(n)VH:L CNTINH:L channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 12-206. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD) and (C(n)V < C(n+1)V) FTM counter MODH:L = C(n+1)VH:L C(n)VH:L CNTINH:L channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 12-207.
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Functional Description FTM counter MODH:L = C(n+1)VH:L C(n)VH:L CNTINH:L channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 not fully 100% duty cycle not fully 0% duty cycle Figure 12-209.
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Chapter 12 FlexTimer Module (FTM) FTM counter C(n+1)VH:L MODH:L CNTINH:L C(n)VH:L channel (n) output with ELSnB:ELSnA = 1:0 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 100% duty cycle Figure 12-211. Channel (n) output if C(n)V and C(n+1)V are not between CNTIN and MOD FTM counter MODH:L C(n+1)VH:L = C(n)VH:L CNTINH:L channel (n) output with ELSnB:ELSnA = 1:0 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 100% duty cycle Figure 12-212.
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Functional Description FTM counter MODH:L C(n+1)VH:L = C(n)VH:L = CNTINH:L channel (n) output with ELSnB:ELSnA = 1:0 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 100% duty cycle Figure 12-213. Channel (n) output if (C(n)V = C(n+1)V = CNTIN) MODH:L = C(n+1)VH:L = C(n)VH:L FTM counter CNTINH:L channel (n) output with ELSnB:ELSnA = 1:0 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 100% duty cycle Figure 12-214.
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Chapter 12 FlexTimer Module (FTM) FTM counter MODH:L C(n+1)VH:L CNTINH:L C(n)VH:L channel (n) output with ELSnB:ELSnA = 1:0 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 100% duty cycle Figure 12-216. Channel (n) output if (C(n)V < CNTIN) and (CNTIN < C(n+1)V < MOD) FTM counter MODH:L C(n)VH:L CNTINH:L C(n+1)VH:L channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 12-217.
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Functional Description FTM counter C(n)VH:L MODH:L C(n+1)VH:L CNTINH:L channel (n) output with ELSnB:ELSnA = 1:0 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 100% duty cycle Figure 12-218. Channel (n) output if (C(n)V > MOD) and (CNTIN < C(n+1)V < MOD) FTM counter C(n+1)VH:L MODH:L C(n)VH:L CNTINH:L channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 12-219.
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Chapter 12 FlexTimer Module (FTM) FTM counter C(n+1)VH:L MODH:L = C(n)VH:L CNTINH:L channel (n) output with ELSnB:ELSnA = 1:0 not fully 0% duty cycle channel (n) output with ELSnB:ELSnA = X:1 not fully 100% duty cycle Figure 12-220. Channel (n) output if (C(n+1)V > MOD) and (CNTIN < C(n)V = MOD) 12.4.8.
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Functional Description channel (n+1) match FTM counter channel (n) match channel (n) output with ELSnB:ELSnA = 1:0 channel (n+1) output with COMP = 0 channel (n+1) output with COMP = 1 Figure 12-221. Channel (n+1) output in complementary mode with (ELSnB:ELSnA = 1:0) channel (n+1) match FTM counter channel (n) match channel (n) output with ELSnB:ELSnA = X:1 channel (n+1) output with COMP = 0 channel (n+1) output with COMP = 1 Figure 12-222.
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Chapter 12 FlexTimer Module (FTM) • If the selected mode is not CPWM mode, then MODH:L registers are updated after both bytes have been written and the FTM counter changes from (MODH:L) to (CNTINH:L). If the FTM counter is a free-running counter, then this update is made when the FTM counter changes from 0xFFFF to 0x0000. • If the selected mode is CPWM mode, then MODH:L registers are updated after both bytes have been written and the FTM counter changes from MODH:L to (MODH:L – 0x0001).
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Functional Description • If the selected mode is output compare mode, then CnVH:L registers are updated according to the SYNCEN bit. If (SYNCEN = 0), then CnVH:L registers are updated after their second byte is written and on the next change of the FTM counter. If (SYNCEN = 1), then CnVH:L registers are updated by PWM synchronization. See CnVH:L registers synchronization. • If the selected mode is not output compare mode and (SYNCEN = 1), then CnVH:L registers are updated by PWM synchronization.
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Chapter 12 FlexTimer Module (FTM) system clock write 1 to TRIG0 bit TRIG0 bit trigger_0 input synchronized trigger_0 by system clock trigger 0 event Notes - All hardware trigger (input signals: trigger_0, trigger_1, and trigger_2) have this same behavior Figure 12-223. Hardware trigger event 12.4.11.2 Software trigger A software trigger event occurs when 1 is written to the SWSYNC bit.
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Functional Description system clock write 1 to SWSYNC bit SWSYNC bit software trigger event PWM synchronization Figure 12-224. Software Trigger event 12.4.11.3 Boundary cycle The CNTMAX and CNTMIN bits select the boundary cycle when the MODH:L and CnVH:L registers are updated with the value of their write buffer by PWM synchronization, except if (PWMSYNC = 0 and REINIT = 1). If CNTMIN = 1, then the boundary cycle is the CNTINH:L value.
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Chapter 12 FlexTimer Module (FTM) Note • PWM synchronization boundary cycle is available only when (CNTMIN = 1). • PWM synchronization with (CNTMAX = 1) is not recommended and its results are not guaranteed. 12.4.11.4 MODH:L registers synchronization The MODH:L synchronization occurs when the MODH:L registers are updated with the value of their write buffer. The synchronization requires both bytes of MODH:L to have been written in one of the following situations.
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Functional Description system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 event selected boundary cycle MODH:L registers are updated if both bytes were written Figure 12-226. MODH:L synchronization when (PWMSYNC = 0), (REINIT = 0), and a hardware trigger was used • If PWMSYNC = 0 and REINIT = 1, then the synchronization is made on the next enabled trigger event. If the trigger event was a software trigger, then the SWSYNC bit is cleared. See the following figure.
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Chapter 12 FlexTimer Module (FTM) system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 event MODH:L registers are updated if both bytes were written Figure 12-228. MODH:L synchronization when (PWMSYNC = 0), (REINIT = 1), and a hardware trigger was used • If PWMSYNC = 1, then the synchronization is made on the next selected boundary cycle after the enabled software trigger event takes place. The SWSYNC bit is cleared on the next selected boundary cycle. See the following figure.
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Functional Description 12.4.11.6 OUTMASK register synchronization Any write to a CHnOM bit updates the OUTMASK write buffer. The CHnOM bit is updated with the value of its corresponding bit in the OUTMASK write buffer according to SYNCHOM and PWMSYNC bits. • If SYNCHOM = 0, then the CHnOM bit is updated with the value of its write buffer equivalent in all rising edges of the system clock. system clock write to CHnOM bit set CHnOM clear CHnOM write buffer of CHnOM bit CHnOM bit Figure 12-230.
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Chapter 12 FlexTimer Module (FTM) system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 event CHnOM bit is updated and TRIG0 bit is cleared Figure 12-232. CHnOM synchronization when (SYNCHOM = 1), (PWMSYNC = 0), and a hardware trigger was used • If SYNCHOM = 1 and PWMSYNC = 1, then this synchronization is made on the next enabled hardware trigger event. The trigger enable bit (TRIGn) is cleared when the enabled hardware trigger n event is detected. See the following figure.
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Functional Description system clock write 1 to SWSYNC bit SWSYNC bit software trigger event FTM counter is reset and channel outputs are forced to their initial value Figure 12-234. FTM counter synchronization when (REINIT = 1), (PWMSYNC = 0), and software trigger was used If the trigger event was a hardware trigger, then the TRIGn bit is cleared. See the following figure.
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Chapter 12 FlexTimer Module (FTM) 12.4.11.8 Summary of PWM synchronization The following table shows the summary of PWM synchronization. Table 12-246. Summary of PWM synchronization Register or bit PWMSYN C REINIT CNTINH:L X X SYNCH CNTMA OM X X X CNTMI N SYNCE Description N X X Changes take effect after the second byte is written. Effect is seen after the next TOF or PWM synchronization.
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Functional Description Table 12-246. Summary of PWM synchronization (continued) Register or bit PWMSYN C REINIT CnVH:L 0 0 X 1 0 1 CnVH:L are updated with their write buffer contents when the counter reaches its maximum value after the enabled hardware or software trigger has occurred. 0 0 X 0 1 1 CnVH:L are updated with their write buffer contents when the counter reaches its minimum value after the enabled hardware or software trigger has occurred.
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Chapter 12 FlexTimer Module (FTM) Table 12-246. Summary of PWM synchronization (continued) Register or bit PWMSYN C REINIT SWSYNC bit 0 0 X 1 0 X SWSYNC bit is cleared when the counter reaches its maximum value after the enabled software trigger has occurred. 0 0 X 0 1 X SWSYNC bit is cleared when the counter reaches its minimum value after the enabled software trigger has occurred. 0 1 X X X X SWSYNC bit is cleared when the enabled software trigger occurs.
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Functional Description For POL(n) = 1, POL(n+1) = 1, and deadtime enabled, a falling edge on the output of channel (n) remains high for the duration of the deadtime delay, after which the falling edge appears on the output. Similarly, when a rising edge is due on the output of channel (n), the channel (n+1) output remains high for the duration of the deadtime delay, after which the channel (n+1) output will have a falling edge.
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Chapter 12 FlexTimer Module (FTM) 12.4.12.1 Deadtime insertion corner cases If (PS[2:0] bits are cleared), (DTPS[1:0] = 0:0 or DTPS[1:0] = 0:1): • and the deadtime delay is greater than or equal to the channel (n) duty cycle ((C(n +1)VH:L – C(n)VH:L) × system clock), then the channel (n) output is always the inactive value (POL(n) bit value).
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Functional Description channel (n+1) match FTM counter channel (n) match channel (n) output (before deadtime insertion) channel (n+1) output (before deadtime insertion) channel (n) output (after deadtime insertion) channel (n+1) output (after deadtime insertion) Figure 12-240. Example of the deadtime insertion (ELSnB:ELSnA = 1:0, POL(n) = 0, and POL(n+1) = 0) when the deadtime delay Is comparable to channels (n) and (n+1) duty cycle 12.4.
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Chapter 12 FlexTimer Module (FTM) the beginning of new PWM cycles FTM counter channel (n) output (before output mask) CHnOM bit channel (n) output (after output mask) configured PWM signal starts to be available in the channel (n) output channel (n) output is disabled Figure 12-241. Output mask The following table shows the output mask result before the polarity control. Table 12-247.
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Functional Description is reset and starts counting up. As long as the new state is stable on the fault input n, the counter continues to increment. If the 5-bit counter overflows and exceeds the value of the FFVAL[3:0] bits, the new fault input n value is validated. It is then transmitted as a pulse edge to the edge detector. If the opposite edge appears on the fault input n signal before validation (counter overflow), the counter is reset. At the next input transition, the counter starts counting again.
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Chapter 12 FlexTimer Module (FTM) If the fault control is enabled (FAULTM[1:0] ≠ 0:0), a fault condition has occurred (rising edge at the logic OR of the enabled fault input) and (FAULTEN = 1), then channel (n) and (n+1) outputs are forced to their safe value (that is, the channel (n) output is forced to the value of POL(n) and the channel (n+1) is forced to the value of POL(n +1)). The fault interrupt is generated when (FAULTF = 1) and (FAULTIE = 1).
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Functional Description 12.4.14.2 Manual fault clearing If the manual fault clearing is selected (FAULTM[1:0] = 0:1 or 1:0), then disabled channel outputs are enabled when the FAULTF bit is cleared and a new PWM cycle begins. See the following figure. It is possible to manually clear a fault by clearing the FAULTF bit, and enable disabled channels regardless of the fault input signal (FAULTIN) (the filter output if the filter is enabled or the synchronizer output if the filter is disabled).
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Chapter 12 FlexTimer Module (FTM) Note Polarity control is available only in combine mode. 12.4.16 Initialization The initialization forces the CHnOI bit value to the channel (n) output when a one is written to the INIT bit. Note • It is recommended to use the initialization only when the FTM counter is disabled (CLKS[1:0] = 0:0). • Initialization is available only in combine mode. 12.4.
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Functional Description the beginning of new PWM cycles FTM counter = C1VH:L FTM counter = C0VH:L FTM counter = C5VH:L FTM counter = C4VH:L FTM counter = C3VH:L FTM counter = C2VH:L match trigger when CH2TRIG=0, CH3TRIG=0, CH4TRIG=0, CH5TRIG=0, CH0TRIG=0, and CH1TRIG=0 match trigger when CH2TRIG=0, CH3TRIG=0, CH4TRIG=0, CH5TRIG=0, CH0TRIG=1, and CH1TRIG=0 match trigger when CH2TRIG=0, CH3TRIG=1, CH4TRIG=1, CH5TRIG=1, CH0TRIG=0, and CH1TRIG=0 match trigger when CH2TRIG=1, CH3TRIG=1, CH4TRIG=1, CH5TRIG=1, CH
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Chapter 12 FlexTimer Module (FTM) • When there is a write to CNTH or CNTL register CNTINH:L = 0x0000 MODH:L = 0x000F CPWMS = 0 system clock FTM counter 0x04 0x05 0x06 0x00 0x01 0x02 0x03 0x04 0x05 0x06 write to CNTH initialization trigger Figure 12-249.
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Functional Description Note Initialization trigger is available only in combine mode. 12.4.20 Capture test mode The capture test mode allows the testing of the CnVH:L registers, the FTM counter, and the interconnection logic between the FTM counter and CnVH:L registers. In this test mode, all channels must be configured for input capture mode (see Input capture mode) and FTM counter must be configured for up-counting (see Up counting).
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Chapter 12 FlexTimer Module (FTM) FTM counter clock set CAPTEST clear CAPTEST write to MODE CAPTEST bit FTM counter 0x1053 0x1054 0x1055 0x1056 0x7856 0x78AC 0x78AD 0x78AE 0x78AF 0x78B0 write 0x78 write to CNTH write 0xAC write to CNTL CH0F bit C0VH:L 0x0300 0x78AC Notes - FTM counter configuration: (FTMEN = 1), (CAPTEST = 1), (CPWMS = 0), (CNTINH:L = 0x0000) and (MODH:L = 0xFFFF) - FTM channel n configuration: input capture mode – (DECAPEN = 0), (COMBINE = 0), and (MSnB:MSnA = 0:0) Figure 1
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Functional Description FTMEN DECAPEN is filter DECAP enabled? MS(n)A ELS(n)B:ELS(n)A ELS(n+1)B:ELS(n+1)A 0 synchronizer channel (n) input system clock D CLK Q D CLK Q CH(n)IE CH(n)F C(n)VH:L[15:0] Dual edge capture mode logic Filter* 1 channel (n) interrupt CH(n+1)IE CH(n+1)F channel (n+1) interrupt C(n+1)VH:L[15:0] FTM counter * Filtering function for dual edge capture mode is only available in the channels 0 and 2 Figure 12-253.
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Chapter 12 FlexTimer Module (FTM) • The CH(n+1)F, CH(n+1)IE, MS(n+1)A, ELS(n+1)B, and ELS(n+1)A bits are channel (n+1) bits. • It is expected that the dual edge capture mode be used with ELS(n)B:ELS(n)A = 0:1 or 1:0, ELS(n+1)B:ELS(n+1)A = 0:1 or 1:0 and the FTM counter in free running counter mode. See Free running counter. 12.4.21.1 One-shot capture mode The one-shot capture mode is selected when (FTMEN = 1), (DECAPEN = 1), and (MS(n)A = 0).
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Functional Description In this mode, it is possible to clear only the CH(n+1)F bit. Therefore, when the CH(n+1)F bit is set again, the latest captured values are available in C(n)VH:L and C(n+1)VH:L registers. For a new sequence of the measurements in the dual edge capture – continuous mode, it is recommended to clear the CH(n)F and CH(n+1) bits to start new measurements. 12.4.21.
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Chapter 12 FlexTimer Module (FTM) 4 FTM counter 12 8 3 7 2 6 1 16 11 10 5 20 15 14 9 13 24 19 18 17 28 23 27 22 26 21 25 channel (n) input (after the filter channel input) DECAPEN bit set DECAPEN DECAP bit set DECAP C(n)VH:L 1 3 5 7 9 15 2 4 6 8 10 16 19 CH(n)F bit clear CH(n)F C(n+1)VH:L 20 22 24 CH(n+1)F bit clear CH(n+1)F problem 1 problem 2 Note: - The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user.
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Functional Description 4 FTM counter 12 8 3 7 2 6 1 16 11 10 5 20 15 14 9 13 24 19 18 17 28 23 27 22 26 21 25 channel (n) input (after the filter channel input) DECAPEN bit set DECAPEN DECAP bit set DECAP C(n)VH:L 1 3 5 7 9 11 15 19 21 23 2 4 6 8 10 12 16 20 22 24 CH(n)F bit clear CH(n)F C(n+1)VH:L CH(n+1)F bit clear CH(n+1)F Note - The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user. Figure 12-255.
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Chapter 12 FlexTimer Module (FTM) enable the measurement of next period. The CH(n)F bit is set when the first rising edge is detected, that is, the edge selected by ELS(n)B:ELS(n)A bits. The CH(n+1)F bit is set and DECAP bit is cleared when the second rising edge is detected, that is, the edge selected by ELS(n+1)B:ELS(n+1)A bits. Both DECAP and CH(n+1)F bits indicate when two selected edges were captured and the C(n)VH:L and C(n+1)VH:L registers are ready for reading.
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Functional Description is set when the second rising edge is detected, that is, the edge selected by ELS(n +1)B:ELS(n+1)A bits. The CH(n+1)F bit indicates when two edges of the period were captured and the C(n)VH:L and C(n+1)VH:L registers are ready for reading.
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Chapter 12 FlexTimer Module (FTM) When a rising edge occurs in the channel (n) input signal, the FTM counter value is captured into channel (n) capture buffer. The channel (n) capture buffer value is transferred to C(n)VH:L registers when a falling edge occurs in the channel (n) input signal. C(n)VH:L registers have the FTM counter value when the previous rising edge occurred, and the channel (n) capture buffer has the FTM counter value when the last rising edge occurred.
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Functional Description 12.4.22 TPM emulation This section describe the FTM features that are selected according to the FTMEN bit. 12.4.22.1 MODH:L and CnVH:L synchronization If (FTMEN = 0), then the MODH:L and CnVH:L registers are updated according to the Update of the registers with write buffers and they are not updated by PWM synchronization. If (FTMEN = 1), then the MODH:L and CnVH:L registers are updated only by PWM synchronization (PWM synchronization). 12.4.22.
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Chapter 12 FlexTimer Module (FTM) 12.4.23 BDM mode When BDM mode is active, the FlexTimer counter and the channels output are frozen. However, the value of FlexTimer counter or the channels output are modified in BDM mode when: • A write of any value to the CNTH or CNTL registers (Counter reset) resets the FTM counter to the value of CNTINH:L and the channels output to their initial value, except for channels in output compare mode.
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Reset overview The following figure shows the FTM behavior after the reset. At the reset (item 1), the FTM counter is disabled (see table "FTM Clock Source Selection"), its value is updated to zero and the pins are not controlled by FTM (table "Mode, Edge, and Level Selection"). After the reset, the FTM should be configured (item 2).
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Chapter 12 FlexTimer Module (FTM) (3) write any value to CNTH or CNTL registers (1) FTM reset FTM counter CLKS[1:0] (4) use of initialization to update the channel output to the zero (5) write 0b01 to CLKS[1:0] XXXX 0x0000 XX 0b00 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 . . .
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FTM Interrupts MC9S08PA60 Reference Manual, Rev. 1, 9/2012 384 Freescale Semiconductor, Inc.
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Chapter 13 8-bit modulo timer (MTIM) 13.1 Introduction The MTIM is a simple 8-bit timer with several software selectable clock sources and a programmable interrupt. For MCUs that have more than one MTIM, the MTIMs are collectively called MTIMx. For example, MTIMx for an MCU with two MTIMs would refer to MTIM1 and MTIM2. For MCUs that have exactly one MTIM, it is always referred to as MTIM. 13.
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Block diagram 13.3.1 MTIM in wait mode The MTIM continues to run in wait mode if enabled before executing the WAIT instruction. Therefore, the MTIM can be used to bring the MCU out of wait mode if the timer overflow interrupt is enabled. For lowest possible current consumption, the MTIM must be stopped by software if not needed as an interrupt source during wait mode. 13.3.2 MTIM in stop mode The MTIM is disabled in stop mode, regardless of the settings before executing the STOP instruction.
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Chapter 13 8-bit modulo timer (MTIM) 13.5 External signal description The MTIM includes one external signal, TCLK, used to input an external clock when selected as the MTIM clock source. The signal properties of TCLK are shown in the following table. Table 13-1. MTIM external signal Signal TCLK Function I/O External clock source input into MTIM I The TCLK input must be synchronized by the bus clock. Also, variations in duty cycle and clock jitter must be accommodated.
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Register definition 13.6.1 MTIM Status and Control Register (MTIMx_SC) MTIM_SC contains the overflow status flag and control bits that are used to configure the interrupt enable, reset the counter, and stop the counter.
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Chapter 13 8-bit modulo timer (MTIM) 13.6.2 MTIM Clock Configuration Register (MTIMx_CLK) MTIM_CLK contains the clock select bits (CLKS) and the prescaler select bits (PS). Address: Base address + 1h offset Bit Read Write Reset 7 6 5 0 0 4 3 2 CLKS 0 0 1 0 0 0 PS 0 0 0 MTIMx_CLK field descriptions Field 7–6 Reserved 5–4 CLKS Description This field is reserved. This read-only field is reserved and always has the value 0.
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Functional description 13.6.3 MTIM Counter Register (MTIMx_CNT) MTIM_CNT is the read-only value of the current MTIM count of the 8-bit counter. Address: Base address + 2h offset Bit 7 6 5 4 Read 3 2 1 0 0 0 0 0 COUNT Write Reset 0 0 0 0 MTIMx_CNT field descriptions Field 7–0 COUNT Description MTIM Count These eight read-only bits contain the current value of the 8-bit counter. Writes have no effect to this register. Reset clears the count to 0x00. 13.6.
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Chapter 13 8-bit modulo timer (MTIM) The MTIM counter (MTIM_CNT) has three modes of operation: stopped, free-running, and modulo. Out of reset, the counter is stopped. If the counter is started without writing a new value to the modulo register, then the counter will be in free-running mode. The counter is in modulo mode when a value other than 0x00 is in the modulo register while the counter is running. After any MCU reset, the counter is stopped and reset to 0x00, and the modulus is set to 0x00.
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Functional description The MTIM allows for an optional interrupt to be generated whenever SC[TOF] is set. To enable the MTIM overflow interrupt, set the MTIM overflow interrupt enable bit (SC[TOIE]). SC[TOIE] must never be written to a 1 while SC[TOF] = 1. Instead, SC[TOF] must be cleared first, then the SC[TOIE] can be set to 1. 13.7.1 MTIM operation example This section shows an example of the MTIM operation as the counter reaches a matching value from the modulo register.
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Chapter 14 Real-time counter (RTC) 14.1 Introduction The real-time counter (RTC) consists of one 16-bit counter, one 16-bit comparator, several binary-based and decimal-based prescaler dividers, three clock sources, one programmable periodic interrupt, and one programmable external toggle pulse output. This module can be used for time-of-day, calendar or any task scheduling functions. It can also serve as a cyclic wakeup from low power modes, stop3 and wait without the need of external components. 14.1.
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Features 14.2 Features Features of the RTC module include: • 16-bit up-counter • 16-bit modulo match limit • Software controllable periodic interrupt on match • Software selectable clock sources for input to prescaler with programmable 16 bit prescaler • XOSC 32.678KHz nominal. • LPO (~1 kHz) • Bus clock 14.2.1 Modes of operation This section defines the RTC operation in stop, wait, and background debug modes. 14.2.1.
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Chapter 14 Real-time counter (RTC) RTCMOD 16-bit modulo 16-bit latch 16-bit modulo 1 D 16-bit comparator EXT CLK LPO CLK CLOCK DIVIDER BUS CLK RTIF Q RTC INTERRUPT REQUEST R 16-bit counter BUS CLK RTIE D Q Q RTCLKS RTCO RTCCNT RTCPS OUTPUT TOGLE Write 1 to RTIF Figure 14-1. Real-time counter (RTC) block diagram 14.3 External signal description RTCO is the output of RTC. After MCU reset, the RTC_SC1[RTCO] is set to high. When the counter is overflow, the output is toggled. 14.
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Register definition 14.4.1 RTC Status and Control Register 1 (RTC_SC1) RTC_SC1 contains the real-time interrupt status flag (RTIF), and the toggle output enable bit (RTCO). Address: 306Ah base + 0h offset = 306Ah Bit Read Write Reset 7 6 5 RTIF RTIE 0 0 0 0 4 RTCO 0 3 2 1 0 0 0 0 0 0 RTC_SC1 field descriptions Field 7 RTIF Description Real-Time Interrupt Flag This status bit indicates the RTC counter register reached the value in the RTC modulo register.
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Chapter 14 Real-time counter (RTC) 14.4.2 RTC Status and Control Register 2 (RTC_SC2) RTC_SC2 contains the clock select bits (RTCLKS) and the prescaler select bits (RTCPS). Address: 306Ah base + 1h offset = 306Bh Bit Read Write Reset 7 6 5 RTCLKS 0 4 3 2 0 0 0 0 1 0 RTCPS 0 0 0 0 RTC_SC2 field descriptions Field 7–6 RTCLKS Description Real-Time Clock Source Select These two read/write bits select the clock source input to the RTC prescaler.
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Register definition 14.4.3 RTC Modulo Register: High (RTC_MODH) RTC_MODH, together with RTC_MODL, indicates the value of the 16-bit modulo value. Address: 306Ah base + 2h offset = 306Ch Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 MODH 0 0 0 0 RTC_MODH field descriptions Field 7–0 MODH Description RTC Modulo High These sixteen read/write bits, MODH and MODL, contain the modulo value used to reset the count to 0x0000 upon a compare match and set the RTIF status bit.
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Chapter 14 Real-time counter (RTC) 14.4.5 RTC Counter Register: High (RTC_CNTH) RTC_CNTH, together with RTC_CNTL, indicates the read-only value of the current RTC count of the 16-bit counter. Address: 306Ah base + 4h offset = 306Eh Bit 7 6 5 4 Read 3 2 1 0 0 0 0 0 CNTH Write Reset 0 0 0 0 RTC_CNTH field descriptions Field 7–0 CNTH Description RTC Count High CNTH and CNTL contain the current value of the 16-bit counter. Writes have no effect to this register.
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Functional description 14.5 Functional description The RTC is composed of a main 16-bit up-counter with a 16-bit modulo register, a clock source selector, and a prescaler block with binary-based and decimal-based selectable values. The module also contains software selectable interrupt logic and toggle logic for pinout. After any MCU reset, the counter is stopped and reset to 0x0000, the modulus register is set to 0x0000, and the prescaler is off.
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Chapter 14 Real-time counter (RTC) transition from the modulo value to 0x0000. The modulo value written to RTC_MODH and RTC_MODL is latched until the RTC counter overflows or the RTC_SC2[RTCPS] is selected non-zero. The RTC allows for an interrupt to be generated whenever RTC_SC1[RTIF] is set. To enable the real-time interrupt, set the real-time interrupt enable bit (RTC_SC1[RTIE]). RTC_SC1[RTIF] is cleared by writing a 1 to RTC_SC1[RTIF].
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Initialization/application information 14.6 Initialization/application information This section provides example code to give some basic direction to a user on how to initialize and configure the RTC module. The example software is implemented in C language. The example below shows how to implement time of day with the RTC using the XOSC clock source to achieve the lowest possible power consumption. Example: 14.6.
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Chapter 15 Serial communications interface (SCI) 15.1 Introduction 15.1.
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Introduction • Loop mode • Single-wire mode 15.1.3 Block diagram The following figure shows the transmitter portion of the SCI.
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Chapter 15 Serial communications interface (SCI) Internal Bus (Write-Only) LOOPS SCID – Tx Buffer RSRC Loop Control Stop M Start 11-BIT Transmit Shift Register 8 7 6 5 4 3 2 1 0 To TxD Pin L lsb H 1 Baud Rate Clock To Receive Data In SHIFT DIRECTION PT Break (All 0s) Parity Generation Preamble (All 1s) PE Shift Enable T8 Load From SCIxD TXINV SCI Controls TxD TE SBK Transmit Control TXDIR TxD Direction TO TxD Pin Logic BRK13 TDRE TIE TC Tx Interrupt Request TCIE Fi
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Register definition SCI memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 3080 SCI Baud Rate Register: High (SCI0_BDH) 8 R/W 00h 15.2.1/406 3081 SCI Baud Rate Register: Low (SCI0_BDL) 8 R/W 04h 15.2.2/407 3082 SCI Control Register 1 (SCI0_C1) 8 R/W 00h 15.2.3/408 3083 SCI Control Register 2 (SCI0_C2) 8 R/W 00h 15.2.4/409 3084 SCI Status Register 1 (SCI0_S1) 8 R C0h 15.2.
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Chapter 15 Serial communications interface (SCI) SCIx_BDH field descriptions Field 7 LBKDIE 6 RXEDGIE 5 SBNS Description LIN Break Detect Interrupt Enable (for LBKDIF) 0 1 Hardware interrupts from SCI_S2[LBKDIF] disabled (use polling). Hardware interrupt requested when SCI_S2[LBKDIF] flag is 1. RxD Input Active Edge Interrupt Enable (for RXEDGIF) 0 1 Hardware interrupts from SCI_S2[RXEDGIF] disabled (use polling). Hardware interrupt requested when SCI_S2[RXEDGIF] flag is 1.
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Register definition 15.2.3 SCI Control Register 1 (SCIx_C1) This read/write register controls various optional features of the SCI system. Address: Base address + 2h offset Bit Read Write Reset 7 6 5 4 3 2 1 0 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0 0 0 0 0 0 0 0 SCIx_C1 field descriptions Field 7 LOOPS Description Loop Mode Select Selects between loop back modes and normal 2-pin full-duplex modes.
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Chapter 15 Serial communications interface (SCI) SCIx_C1 field descriptions (continued) Field 1 PE Description Parity Enable Enables hardware parity generation and checking. When parity is enabled, the most significant bit (msb) of the data character, eighth or ninth data bit, is treated as the parity bit. 0 1 0 PT No hardware parity generation or checking. Parity enabled. Parity Type Provided parity is enabled (PE = 1), this bit selects even or odd parity.
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Register definition SCIx_C2 field descriptions (continued) Field Description TE must be 1 to use the SCI transmitter. When TE is set, the SCI forces the TxD pin to act as an output for the SCI system. When the SCI is configured for single-wire operation (LOOPS = RSRC = 1), TXDIR controls the direction of traffic on the single SCI communication line (TxD pin). TE can also queue an idle character by clearing TE then setting TE while a transmission is in progress.
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Chapter 15 Serial communications interface (SCI) SCIx_S1 field descriptions Field 7 TDRE Description Transmit Data Register Empty Flag TDRE is set out of reset and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read SCI_S1 with TDRE set and then write to the SCI data register (SCI_D).
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Register definition SCIx_S1 field descriptions (continued) Field Description within any bit time in the frame, the flag NF is set at the same time as RDRF is set for the character. To clear NF, read SCI_S1 and then read the SCI data register (SCI_D). 0 1 1 FE No noise detected. Noise detected in the received character in SCI_D. Framing Error Flag FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop bits was expected.
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Chapter 15 Serial communications interface (SCI) SCIx_S2 field descriptions (continued) Field Description 0 1 6 RXEDGIF RxD Pin Active Edge Interrupt Flag RXEDGIF is set when an active edge, falling if RXINV = 0, rising if RXINV=1, on the RxD pin occurs. RXEDGIF is cleared by writing a 1 to it. 0 1 5 Reserved 4 RXINV No LIN break character has been detected. LIN break character has been detected. No active edge on the receive pin has occurred. An active edge on the receive pin has occurred.
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Register definition 15.2.7 SCI Control Register 3 (SCIx_C3) Address: Base address + 6h offset Bit Read 7 R8 Write Reset 0 6 5 4 3 2 1 0 T8 TXDIR TXINV ORIE NEIE FEIE PEIE 0 0 0 0 0 0 0 SCIx_C3 field descriptions Field Description 7 R8 Ninth Data Bit for Receiver 6 T8 Ninth Data Bit for Transmitter 5 TXDIR When the SCI is configured for 9-bit data (M = 1), R8 can be thought of as a ninth receive data bit to the left of the msb of the buffered data in the SCI_D register.
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Chapter 15 Serial communications interface (SCI) SCIx_C3 field descriptions (continued) Field 1 FEIE Description Framing Error Interrupt Enable This bit enables the framing error flag (FE) to generate hardware interrupt requests. 0 1 0 PEIE FE interrupts disabled; use polling). Hardware interrupt requested when FE is set. Parity Error Interrupt Enable This bit enables the parity error flag (PF) to generate hardware interrupt requests. 0 1 PF interrupts disabled; use polling).
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Functional description SCIx_D field descriptions (continued) Field 0 R0T0 Description Read receive data buffer 0 or write transmit data buffer 0. 15.3 Functional description The SCI allows full-duplex, asynchronous, NRZ serial communication among the MCU and remote devices, including other MCUs. The SCI comprises a baud rate generator, transmitter, and receiver block. The transmitter and receiver operate independently, although they use the same baud rate generator.
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Chapter 15 Serial communications interface (SCI) format. Although baud rate modulo divider settings do not always produce baud rates that exactly match standard rates, it is normally possible to get within a few percent, which is acceptable for reliable communications. 15.3.2 Transmitter functional description This section describes the overall block diagram for the SCI transmitter, as well as specialized functions for sending break and idle characters.
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Functional description soon as the shifter is available. If SCI_C2[SBK] remains 1 when the queued break moves into the shifter, synchronized to the baud rate clock, an additional break character is queued. If the receiving device is another Freescale Semiconductor SCI, the break characters are received as 0s in all eight data bits and a framing error (SCI_S1[FE] = 1) occurs. When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers.
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Chapter 15 Serial communications interface (SCI) The receiver input is inverted by setting SCI_S2[RXINV]. The receiver is enabled by setting the SCI_C2[RE] bit. Character frames consist of a start bit of logic 0, eight (or nine) data bits (lsb first), and one (or two) stop bits of logic 1. For information about 9-bit data mode, refer to 8- and 9-bit data modes. For the remainder of this discussion, assume the SCI is configured for normal 8-bit data mode.
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Functional description The falling edge detection logic continuously looks for falling edges. If an edge is detected, the sample clock is resynchronized to bit times. This improves the reliability of the receiver in the presence of noise or mismatched baud rates. It does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame.
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Chapter 15 Serial communications interface (SCI) The idle-line type (SCI_C1[ILT]) control bit selects one of two ways to detect an idle line. When SCI_C1[ILT] is cleared, the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward the full character time of idle. When SCI_C1[ILT] is set, the idle bit counter does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message.
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Functional description interrupts, software polling may be used to monitor the SCI_S1[TDRE] and SCI_S1[TC] status flags if the corresponding SCI_C2[TIE] or SCI_C2[TCIE] local interrupt masks are cleared. When a program detects that the receive data register is full (SCI_S1[RDRF] = 1), it gets the data from the receive data register by reading SCI_D. The SCI_S1[RDRF] flag is cleared by reading SCIxS1 while SCI_S1[RDRF] is set and then reading SCI_D.
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Chapter 15 Serial communications interface (SCI) For coherent writes to the transmit data buffer, write to the SCI_C3[T8] bit before writing to SCI_D. If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character, it is not necessary to write to SCI_C3[T8] again. When data is transferred from the transmit data buffer to the transmit shifter, the value in SCI_C3[T8] is copied at the same time data is transferred from SCI_D to the shifter.
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Functional description In single-wire mode, the SCI_C3[TXDIR] bit controls the direction of serial data on the TxD pin. When SCI_C3[TXDIR] is cleared, the TxD pin is an input to the SCI receiver and the transmitter is temporarily disconnected from the TxD pin so an external device can send serial data to the receiver.
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Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI) 16.1 Introduction The serial peripheral interface (SPI) module provides for full-duplex, synchronous, serial communication between the MCU and peripheral devices. These peripheral devices can include other microcontrollers, analog-to-digital converters, shift registers, sensors, and memories, among others. The SPI runs at a baud rate up to the bus clock divided by two in master mode and up to the bus clock divided by four in slave mode.
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Introduction • Mode fault error flag with CPU interrupt capability • Control of SPI operation during wait mode • Selectable MSB-first or LSB-first shifting 16.1.2 Modes of Operation The SPI functions in three modes, run, wait, and stop. • Run Mode This is the basic mode of operation. • Wait Mode SPI operation in wait mode is a configurable low power mode, controlled by the SPISWAI bit located in the SPIx_C2 register. In wait mode, if the SPISWAI bit is clear, the SPI operates like in Run Mode.
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Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI) 16.1.3.1 SPI System Block Diagram The following figure shows the SPI modules of two MCUs connected in a master-slave arrangement. The master device initiates all SPI data transfers. During a transfer, the master shifts data out (on the MOSI pin) to the slave while simultaneously shifting data in (on the MISO pin) from the slave. The transfer effectively exchanges the data that was in the SPI shift registers of the two SPI systems.
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External Signal Description In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all MOSI pins together. Peripheral devices often use slightly different names for these pins.
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Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI) 16.2.1 SPSCK — SPI Serial Clock When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master, this pin is the serial clock output. 16.2.2 MOSI — Master Data Out, Slave Data In When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data output. When the SPI is enabled as a slave and SPC0 is 0, this pin is the serial data input.
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Register Definition 16.3 Register Definition The SPI has 8-bit registers to select SPI options, to control baud rate, to report SPI status, to hold an SPI data match value, and for transmit/receive data. SPI memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 3098 SPI control register 1 (SPI0_C1) 8 R/W 04h 16.3.1/430 3099 SPI control register 2 (SPI0_C2) 8 R/W 00h 16.3.2/432 309A SPI baud rate register (SPI0_BR) 8 R/W 00h 16.3.
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Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI) SPI0_C1 field descriptions (continued) Field Description 0 1 5 SPTIE SPI transmit interrupt enable This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). An interrupt occurs when the SPI transmit buffer is empty (SPTEF is set). 0 1 4 MSTR Interrupts from SPTEF inhibited (use polling) When SPTEF is 1, hardware interrupt requested Master/slave mode select This bit selects master or slave mode operation.
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Register Definition 16.3.2 SPI control register 2 (SPIx_C2) This read/write register is used to control optional features of the SPI system. Bit 6 is not implemented and always reads 0.
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Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI) SPI0_C2 field descriptions (continued) Field 0 SPC0 Description SPI pin control 0 This bit enables bidirectional pin configurations. 0 SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. 1 In slave mode of operation: MISO is slave out and MOSI is slave in. SPI configured for single-wire bidirectional operation (pin mode is bidirectional).
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Register Definition SPI0_BR field descriptions (continued) Field 3–0 SPR[3:0] Description SPI baud rate divisor This 4-bit field selects one of nine divisors for the SPI baud rate divider. The input to this divider comes from the SPI baud rate prescaler. Refer to the description of “SPI Baud Rate Generation” for details.
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Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI) SPI0_S field descriptions (continued) Field 5 SPTEF Description SPI transmit buffer empty flag This bit is set when the transmit data buffer is empty. SPTEF is cleared by reading the S register with SPTEF set and then writing a data value to the transmit buffer at D. The S register must be read with SPTEF set to 1 before writing data to the D register; otherwise, the D write is ignored.
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Functional Description Address: 3098h base + 5h offset = 309Dh Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 Bits[7:0] 0 0 0 0 SPI0_D field descriptions Field 7–0 Bits[7:0] Description Data (low byte) 16.3.6 SPI match register (SPIx_M) This register contains the hardware compare value. When the value received in the SPI receive data buffer equals this hardware compare value, the SPI match flag (SPMF) sets.
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Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI) • Master out/slave in (MOSI) • Master in/slave out (MISO) An SPI transfer is initiated in the master SPI device by reading the SPI status register (SPIx_S) when SPTEF = 1 and then writing data to the transmit data buffer (write to SPIxD ). When a transfer is complete, received data is moved into the receive data buffer. The SPIxD register acts as the SPI receive data buffer for reads and as the SPI transmit data buffer for writes.
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Functional Description • If MODFEN and SSOE bit are set, the SS pin is configured as slave select output. The SS output becomes low during each transmission and is high when the SPI is in idle state. If MODFEN is set and SSOE is cleared, the SS pin is configured as input for detecting mode fault error. If the SS input becomes low this indicates a mode fault error where another master tries to drive the MOSI and SPSCK lines.
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Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI) The SS pin is the slave select input. Before a data transmission occurs, the SS pin of the slave SPI must be low. SS must remain low until the transmission is complete . If SS goes high, the SPI is forced into idle state.
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Functional Description 16.4.4 SPI Clock Formats To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses between two different clock phase relationships between the clock and data. The following figure shows the clock formats when CPHA = 1.
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Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI) BIT TIME # (REFERENCE) 1 2 ... 6 7 8 SPSCK (CPOL = 0) SPSCK (CPOL = 1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST LSB FIRST BIT 7 BIT 0 BIT 6 BIT 1 ... ... BIT 2 BIT 5 BIT 1 BIT 6 BIT 0 BIT 7 MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure 16-15. SPI Clock Formats (CPHA = 1) When CPHA = 1, the slave begins to drive its MISO output when SS goes to active low, but the data is not defined until the first SPSCK edge.
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Functional Description Between these two successive transmissions, no pause is inserted; the SS pin remains low. The following figure shows the clock formats when CPHA = 0. At the top of the figure, the eight bit times are shown for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last SPSCK edge. The MSB first and LSB first lines show the order of SPI data bits depending on the setting in LSBFE.
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Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI) When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB depending on LSBFE) when SS goes to active low. The first SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively.
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Functional Description 16.4.6.1 SS Output The SS output feature automatically drives the SS pin low during transmission to select external devices and drives the SS pin high during idle to deselect external devices. When the SS output is selected, the SS output pin is connected to the SS input pin of the external device. The SS output is available only in master mode during normal SPI operation by asserting the SSOE and MODFEN bits as shown in the description of the C1[SSOE] bit.
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Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI) SS is the input or output for the master mode, and it is always the input for the slave mode. The bidirectional mode does not affect SPSCK and SS functions. Note In bidirectional master mode, with the mode fault feature enabled, both data pins MISO and MOSI can be occupied by the SPI, though MOSI is normally used for transmissions in bidirectional mode and MISO is not used by the SPI.
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Functional Description The mode fault flag is cleared automatically by a read of the SPI Status Register (with MODF set) followed by a write to SPI Control Register 1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again. 16.4.8 Low Power Mode Options This section describes the low power mode options. 16.4.8.1 SPI in Run Mode In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state.
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Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI) Note Care must be taken when expecting data from a master while the slave is in a wait mode or a stop mode where the peripheral bus clock is stopped but internal logic states are retained. Even though the shift register continues to operate, the rest of the SPI is shut down (that is, an SPRF interrupt is not generated until an exit from stop or wait mode).
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Functional Description 16.4.10 Interrupts The SPI originates interrupt requests only when the SPI is enabled (the SPE bit in the SPIx_C1 register is set). The following is a description of how the SPI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt priority are chip dependent. Four flag bits, three interrupt mask bits, and one interrupt vector are associated with the SPI system.
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Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI) 16.4.10.3 SPTEF SPTEF occurs when the SPI transmit buffer is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process that is described in the SPI Status Register details. 16.4.10.4 SPMF SPMF occurs when the data in the receive data buffer is equal to the data in the SPI match register. 16.
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Initialization/Application Information 16.5.2 Pseudo-Code Example In this example, the SPI module will be set up for master mode with only hardware match interrupts enabled. The SPI will run at a maximum baud rate of bus clock divided by 2. Clock phase and polarity will be set for an active-high SPI clock where the first edge on SPSCK occurs at the start of the first cycle of a data transfer.
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Chapter 16 8-Bit Serial Peripheral Interface (8-bit SPI) SPIx_M = 0xXX Holds bits 0–7 of the hardware match buffer. SPIx_D = 0xxx Holds bits 0–7 of the data to be transmitted by the transmit buffer and received by the receive buffer. RESET INITIALIZE SPI SPIx_C1 = 0x54 SPIx_C2 = 0x80 SPIx_BR = 0x00 YES SPTEF = 1 ? NO YES WRITE TO SPIx_D SPRF = 1 ? NO YES READ SPIx_D SPMF = 1 ? NO YES READ SPMF WHILE SET TO CLEAR FLAG, THEN WRITE A 1 TO IT CONTINUE Figure 16-18.
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Initialization/Application Information MC9S08PA60 Reference Manual, Rev. 1, 9/2012 452 Freescale Semiconductor, Inc.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) 17.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The serial peripheral interface (SPI) module provides for full-duplex, synchronous, serial communication between the MCU and peripheral devices. These peripheral devices can include other microcontrollers, analog-to-digital converters, shift registers, sensors, and memories, among others.
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Introduction • Double-buffered transmit and receive data register • Serial clock phase and polarity options • Slave select output • Mode fault error flag with CPU interrupt capability • Control of SPI operation during wait mode • Selectable MSB-first or LSB-first shifting • Programmable 8- or 16-bit data transmission length • Receive data buffer hardware match feature • 64-bit FIFO mode for high speed/large amounts of data transfers 17.1.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) The SPI is completely disabled in stop modes where the peripheral bus clock is stopped and internal logic states are not retained. When the CPU wakes from these stop modes, all SPI register content is reset. Detailed descriptions of operating modes appear in Low Power Mode Options. 17.1.
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Introduction 17.1.3.2 SPI Module Block Diagram The following is a block diagram of the SPI module. The central element of the SPI is the SPI shift register. Data is written to the double-buffered transmitter (write to SPIx_DH:SPIx_DL) and gets transferred to the SPI shift register at the start of a data transfer. After shifting in 8 bits or 16 bits (as determined by the SPIMODE bit) of data, the data is transferred into the double-buffered receiver where it can be read from SPIx_DH:SPIx_DL.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) PIN CONTROL M SPE Tx FIFO (64 bits deep) MOSI (MOMI) S Tx BUFFER (WRITE DH:DL) ENABLE SPI SYSTEM M SPI SHIFT REGISTER SHIFT OUT SHIFT IN 8 OR 16 Rx BUFFER (READ DH:DL) BIT MODE SPIMODE FIFOMODE LSBFE SPC0 Rx FIFO (64 bits deep) SHIFT DIRECTION BIDIROE SHIFT Rx BUFFER Tx BUFFER CLOCK FULL EMPTY MASTER CLOCK BUS RATE CLOCK SPI BR CLOCK LOGIC CLOCK GENERATOR MSTR MISO (SISO) S SLAVE CLOCK MASTER/SLAVE M SPSCK S MASTER/ SLAVE M
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External Signal Description 17.2.1 SPSCK — SPI Serial Clock When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master, this pin is the serial clock output. 17.2.2 MOSI — Master Data Out, Slave Data In When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data output. When the SPI is enabled as a slave and SPC0 is 0, this pin is the serial data input.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) 17.3 Memory Map and Register Descriptions The SPI has 8-bit registers to select SPI options, to control baud rate, to report SPI status, to hold an SPI data match value, and for transmit/receive data. SPI memory map Address offset (hex) Absolute address (hex) 0 30A0 SPI control register 1 (SPI1_C1) 8 1 30A1 SPI control register 2 (SPI1_C2) 2 30A2 3 Width Access (in bits) Reset value Section/ page R/W 04h 17.3.
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Memory Map and Register Descriptions SPI1_C1 field descriptions (continued) Field Description 0 1 6 SPE Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are enabled (when FIFOMODE is 1) SPI system enable This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE is cleared, the SPI is disabled and forced into an idle state, and all status bits in the S register are reset.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) SPI1_C1 field descriptions (continued) Field Description 0 1 When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When MODFEN is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input. When MODFEN is 0: In master mode, SS pin function is general-purpose I/O (not SPI).
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Memory Map and Register Descriptions SPI1_C2 field descriptions (continued) Field 4 MODFEN Description Master mode-fault function enable When the SPI is configured for slave mode, this bit has no meaning or effect. (The SS pin is the slave select input.) In master mode, this bit determines how the SS pin is used. For details, refer to the description of the SSOE bit in the C1 register.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) 17.3.3 SPI baud rate register (SPIx_BR) Use this register to set the prescaler and bit rate divisor for an SPI master. This register may be read or written at any time. Address: 30A0h base + 2h offset = 30A2h Bit 7 Read Write Reset 0 6 5 4 3 2 SPPR[2:0] 0 0 0 1 0 0 0 SPR[3:0] 0 0 0 SPI1_BR field descriptions Field Description 7 Reserved This field is reserved. This read-only field is reserved and always has the value 0.
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Memory Map and Register Descriptions 17.3.4 SPI status register (SPIx_S) This register contains read-only status bits. Writes have no meaning or effect. When the FIFO is supported and enabled (FIFOMODE is 1): This register has four flags that provide mechanisms to support an 8-byte FIFO mode: RNFULLF, TNEARF, TXFULLF, and RFIFOEF.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) SPI1_S field descriptions (continued) Field Description When FIFOMODE is 1: This bit indicates the status of the read FIFO when FIFOMODE is enabled. The SPRF is set when the read FIFO has received 64 bits (4 words or 8 bytes) of data from the shifter and there have been no CPU reads of the SPI data (DH:DL) register. SPRF is cleared by reading the SPI data register, which empties the FIFO assuming another SPI message is not received.
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Memory Map and Register Descriptions SPI1_S field descriptions (continued) Field 3 RNFULLF Description Receive FIFO nearly full flag This flag is set when more than three 16-bit words or six 8-bit bytes of data remain in the receive FIFO, provided C3[4] is 0, or when more than two 16-bit words or four 8-bit bytes of data remain in the receive FIFO, provided C3[4] is 1. It has no function if FIFOMODE is not present or is 0.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) 17.3.5 SPI data register high (SPIx_DH) Refer to the description of the DL register. Address: 30A0h base + 4h offset = 30A4h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 Bits[15:8] 0 0 0 0 SPI1_DH field descriptions Field 7–0 Bits[15:8] Description Data (high byte) 17.3.6 SPI data register low (SPIx_DL) This register, together with the DH register, is both the input and output register for SPI data.
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Memory Map and Register Descriptions In 16-bit mode, reading either byte (the DH or DL register) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. Writing to either byte (the DH or DL register) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the transmit data buffer.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) In 16-bit mode, reading either byte (the MH or ML register) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. Writing to either byte (the MH or ML register) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent value into the SPI match registers.
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Memory Map and Register Descriptions SPI1_C3 field descriptions Field 7–6 Reserved 5 TNEAREF_ MARK Description This field is reserved. This read-only field is reserved and always has the value 0. Transmit FIFO nearly empty watermark This bit selects the mark after which the TNEAREF flag is asserted. 0 1 4 RNFULLF_ MARK Receive FIFO nearly full watermark This bit selects the mark after which the RNFULLF flag is asserted.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) The register has four bits dedicated to clearing the interrupts. Writing 1 to these bits clears the corresponding interrupts if the INTCLR bit in the C3 register is 1. Reading these bits always returns 0. This register also has two read-only bits to indicate the transmit FIFO and receive FIFO overrun conditions. When the receive FIFO is full and data is received, RXFOF is set.
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Functional Description SPI1_CI field descriptions (continued) Field Description Writing 1 to this bit clears the TNEAREF interrupt provided that C3[3] is set. 2 RNFULLFCI Receive FIFO nearly full flag clear interrupt Writing 1 to this bit clears the RNFULLF interrupt provided that C3[3] is set. 1 SPTEFCI Transmit FIFO empty flag clear interrupt 0 SPRFCI Receive FIFO full flag clear interrupt Writing 1 to this bit clears the SPTEF interrupt provided that C3[3] is set.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) The SPI can be configured to operate as a master or as a slave. When the MSTR bit in SPI Control Register 1 is set, master mode is selected; when the MSTR bit is clear, slave mode is selected. 17.4.2 Master Mode The SPI operates in master mode when the MSTR bit is set. Only a master SPI module can initiate transmissions. A transmission begins by reading the SPIx_S register while SPTEF = 1 and writing to the master SPI data registers.
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Functional Description delay, SPSCK is started within the master. The rest of the transfer operation differs slightly, depending on the clock format specified by the SPI clock phase bit, CPHA, in SPI Control Register 1 (see SPI Clock Formats). Note A change of the bits CPOL, CPHA, SSOE, LSBFE, MODFEN, SPC0, BIDIROE with SPC0 set, SPIMODE, FIFOMODE, SPPR2-SPPR0 and SPR3-SPR0 in master mode abort a transmission in progress and force the SPI into idle state.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) Note When peripherals with duplex capability are used, take care not to simultaneously enable two receivers whose serial outputs drive the same system slave's serial data output line. As long as no more than one slave device drives the system slave's serial data output line, it is possible for several slaves to receive the same transmission from a master, although the master would not receive return information from all of the receiving slaves.
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Functional Description IPBus (ips_rdata[7:0]) Read Access SPI_REG_BLOCK spidh:l_rx_reg SPI Data Register FIFO depth = 8 bytes RX- FIFO FIFO Ctrlr SPI_CORE_SHFR Load Control shfr_rx_reg Figure 17-23. SPIH:L read side structural overview in FIFO mode IPBus (ips_rdata[7:0]) Read Access SPI_REG_BLOCK SPI Data Register spidh:l_tx_reg TX- FIFO FIFO Ctrlr FIFO depth = 8 bytes SPI_CORE_SHFR Read Control shfr_tx_reg Figure 17-24. SPIH:L write side structural overview in FIFO mode 17.4.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) In 16-bit mode (SPIMODE = 1), the SPI Data Register is comprised of two bytes: SPIx_DH and SPIx_DL. Reading either byte (SPIx_DH or SPIx_DL) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. Writing to either byte (SPIx_DH or SPIx_DL) latches the value into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the transmit data buffer.
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Functional Description input of a master. The MOSI waveform applies to the MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies to the slave select output from a master (provided MODFEN and SSOE = 1). The master SS output goes to active low one-half SPSCK cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. The SS IN waveform applies to the slave select input of a slave.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) When CPHA = 1, the slave's SS input is not required to go to its inactive high level between transfers. In this clock format, a back-to-back transmission can occur, as follows: 1. A transmission is in progress. 2. A new data byte is written to the transmit buffer before the in-progress transmission is complete. 3. When the in-progress transmission is complete, the new, ready data byte is transmitted immediately.
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Functional Description BIT TIME # (REFERENCE) 1 2 ... 6 7 8 SPSCK (CPOL = 0) SPSCK (CPOL = 1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST LSB FIRST BIT 7 BIT 0 BIT 6 BIT 1 ... ... BIT 2 BIT 5 BIT 1 BIT 6 BIT 0 BIT 7 MISO (SLAVE OUT) SS OUT (MASTER) SS IN (SLAVE) Figure 17-26. SPI Clock Formats (CPHA = 0) When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB depending on LSBFE) when SS goes to active low.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking place. In the other cases, the divider is disabled to decrease IDD current. The baud rate divisor equation is as follows (except those reserved combinations in the SPI Baud Rate Divisor table).
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Functional Description 17.4.8.2 Bidirectional Mode (MOMI or SISO) The bidirectional mode is selected when the SPC0 bit is set in SPI Control Register 2 (see the following table). In this mode, the SPI uses only one serial data pin for the interface with one or more external devices. The MSTR bit decides which pin to use. The MOSI pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) 17.4.9 Error Conditions The SPI module has one error condition: the mode fault error. 17.4.9.1 Mode Fault Error If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may be trying to drive the MOSI and SPSCK lines simultaneously.
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Functional Description 17.4.10.2 SPI in Wait Mode SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI Control Register 2. • If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode. • If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode. • If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) 17.4.10.3 SPI in Stop Mode Operation in a stop mode where the peripheral bus clock is stopped but internal logic states are retained depends on the SPI system. The stop mode does not depend on the SPISWAI bit. Upon entry to this type of stop mode, the SPI module clock is disabled (held high or low). • If the SPI is in master mode and exchanging data when the CPU enters the stop mode, the transmission is frozen until the CPU exits stop mode.
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Functional Description service routine (ISR) should check the flag bits to determine which event caused the interrupt. The service routine should also clear the flag bit(s) before returning from the ISR (usually near the beginning of the ISR). 17.4.12.1 MODF MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see the description of the C1[SSOE] bit).
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) 17.4.12.4 SPMF SPMF occurs when the data in the receive data buffer is equal to the data in the SPI match register. In 8-bit mode, SPMF is set only after bits 7–0 in the receive data buffer are determined to be equivalent to the value in SPIx_ML. In 16-bit mode, SPMF is set after bits 15–0 in the receive data buffer are determined to be equivalent to the value in SPIx_MH:SPIx_ML. 17.4.12.
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Initialization/Application Information 1. Update control register 1 (SPIx_C1) to enable the SPI and to control interrupt enables. This register also sets the SPI as master or slave, determines clock phase and polarity, and configures the main SPI options. 2. Update control register 2 (SPIx_C2) to enable additional SPI functions such as the SPI match interrupt feature, the master mode-fault function, and bidirectional mode output as well as to control 8- or 16-bit mode selection and other optional features.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) SPIx_C2 = 0xC0(%11000000) Bit 2 = 0 Reserved Bit 1 SPISWAI = 0 SPI clocks operate in wait mode Bit 0 SPC0 = 0 uses separate pins for data input and output Bit 7 = 0 Reserved Bit 6:4 = 000 Sets prescale divisor to 1 Bit 3:0 = 0000 Sets baud rate divisor to 2 SPIx_BR = 0x00(%00000000) SPIx_S = 0x00(%00000000) Bit 7 SPRF = 0 Flag is set when receive data buffer is full Bit 6 SPMF = 0 Flag is set when SPIx_MH/ML = rece
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Initialization/Application Information RESET INITIALIZE SPI SPIxC1 = 0x54 SPIxC2 = 0xC0 SPIxBR = 0x00 SPIxMH = 0xXX YES SPTEF = 1 ? NO YES WRITE TO SPIxDH:SPIxDL SPRF = 1 ? NO YES READ SPIxDH:SPIxDL SPMF = 1 ? NO YES READ SPMF WHILE SET TO CLEAR FLAG, THEN WRITE A 1 TO IT CONTINUE Figure 17-28. Initialization Flowchart Example for SPI Master Device in 16-bit Mode for FIFOMODE = 0 MC9S08PA60 Reference Manual, Rev. 1, 9/2012 490 Freescale Semiconductor, Inc.
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Chapter 17 16-Bit Serial Peripheral Interface (16-Bit SPI) RESET INITIALIZE SPI SPIxC1 = 0x54 SPIxC2 = 0xC0 SPIxBR = 0x00 SPIxMH = 0xXX Set FIFOMODE WRITE TO SPIxDH:SPIxDL YES TXFULLF = 1 ? YES RNFULLF = 1/ SPRF = 1 ? YES READ SPIxDH:SPIxDL RFIFOEF = 1 ? YES CONTINUE Figure 17-29. Initialization Flowchart Example for SPI Master Device in 16-bit Mode for FIFOMODE = 1 MC9S08PA60 Reference Manual, Rev. 1, 9/2012 Freescale Semiconductor, Inc.
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Initialization/Application Information MC9S08PA60 Reference Manual, Rev. 1, 9/2012 492 Freescale Semiconductor, Inc.
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Chapter 18 Inter-Integrated Circuit (I2C) 18.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The inter-integrated circuit (I2C, I2C, or IIC) module provides a method of communication between a number of devices. The interface is designed to operate up to 100 kbit/s with maximum bus loading and timing. The I2C device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading.
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Introduction • • • • • 10-bit address extension Support for System Management Bus (SMBus) Specification, version 2 Programmable glitch input filter Low power mode wakeup on slave address match Range slave address support 18.1.2 Modes of operation The I2C module's operation in various low power modes is as follows: • Run mode: This is the basic mode of operation. To conserve power in this mode, disable the module.
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Chapter 18 Inter-Integrated Circuit (I2C) Address Module Enable Write/Read Interrupt ADDR_DECODE DATA_MUX CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG Input Sync START STOP Arbitration Control Clock Control In/Out Data Shift Register Address Compare SDA SCL Figure 18-1. I2C Functional block diagram 18.2 I2C signal descriptions The signal properties of I2C are shown in the following table. Table 18-1.
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Memory map and register descriptions I2C memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 3070 I2C Address Register 1 (I2C_A1) 8 R/W 00h 18.3.1/496 3071 I2C Frequency Divider register (I2C_F) 8 R/W 00h 18.3.2/496 3072 I2C Control Register 1 (I2C_C1) 8 R/W 00h 18.3.3/498 3073 I2C Status register (I2C_S) 8 R/W 80h 18.3.4/499 3074 I2C Data I/O register (I2C_D) 8 R/W 00h 18.3.
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Chapter 18 Inter-Integrated Circuit (I2C) I2C_F field descriptions Field 7–6 MULT Description The MULT bits define the multiplier factor mul. This factor is used along with the SCL divider to generate the I2C baud rate. 00 01 10 11 5–0 ICR mul = 1 mul = 2 mul = 4 Reserved ClockRate Prescales the bus clock for bit rate selection. This field and the MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold time, and the SCL stop hold time.
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Memory map and register descriptions 18.3.3 I2C Control Register 1 (I2C_C1) Address: 3070h base + 2h offset = 3072h Bit Read Write Reset 7 6 5 4 3 IICEN IICIE MST TX TXAK 0 0 0 0 0 2 0 RSTA 0 1 WUEN 0 0 0 0 I2C_C1 field descriptions Field 7 IICEN Description I2C Enable Enables I2C module operation. 0 1 6 IICIE I2C Interrupt Enable Enables I2C interrupt requests.
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Chapter 18 Inter-Integrated Circuit (I2C) I2C_C1 field descriptions (continued) Field Description 2 RSTA Repeat START 1 WUEN Wakeup Enable Writing a one to this bit generates a repeated START condition provided it is the current master. This bit will always be read as zero. Attempting a repeat at the wrong time results in loss of arbitration. The I2C module can wake the MCU from low power mode with no peripheral bus running when slave address matching occurs. 0 1 0 Reserved Normal operation.
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Memory map and register descriptions I2C_S field descriptions (continued) Field Description 0 1 5 BUSY Bus Busy Indicates the status of the bus regardless of slave or master mode. This bit is set when a START signal is detected and cleared when a STOP signal is detected. 0 1 4 ARBL Bus is idle Bus is busy Arbitration Lost This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared by software, by writing a one to it.
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Chapter 18 Inter-Integrated Circuit (I2C) 18.3.5 I2C Data I/O register (I2C_D) Address: 3070h base + 4h offset = 3074h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 DATA 0 0 0 0 I2C_D field descriptions Field 7–0 DATA Description Data In master transmit mode, when data is written to this register, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
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Memory map and register descriptions I2C_C2 field descriptions (continued) Field 6 ADEXT Description Address Extension Controls the number of bits used for the slave address. 0 1 7-bit address scheme 10-bit address scheme 5 Reserved This field is reserved. This read-only field is reserved and always has the value 0. 4 Reserved This field is reserved. This read-only field is reserved and always has the value 0.
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Chapter 18 Inter-Integrated Circuit (I2C) 18.3.8 I2C Range Address register (I2C_RA) Address: 3070h base + 7h offset = 3077h Bit Read Write Reset 7 6 5 4 3 2 1 RAD 0 0 0 0 0 0 0 0 0 0 I2C_RA field descriptions Field 7–1 RAD 0 Reserved Description Range Slave Address This field contains the slave address to be used by the I2C module. The field is used in the 7-bit address scheme. Any nonzero write enables this register.
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Memory map and register descriptions I2C_SMB field descriptions Field 7 FACK Description Fast NACK/ACK Enable For SMBus packet error checking, the CPU must be able to issue an ACK or NACK according to the result of receiving data byte. 0 1 6 ALERTEN An ACK or NACK is sent on the following receiving data byte Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
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Chapter 18 Inter-Integrated Circuit (I2C) I2C_SMB field descriptions (continued) Field 0 SHTF2IE Description SHTF2 Interrupt Enable Enables SCL high and SDA low timeout interrupt. 0 1 SHTF2 interrupt is disabled SHTF2 interrupt is enabled 18.3.
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Functional description 18.3.12 I2C SCL Low Timeout Register Low (I2C_SLTL) Address: 3070h base + Bh offset = 307Bh Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 SSLT[7:0] 0 0 0 0 I2C_SLTL field descriptions Field 7–0 SSLT[7:0] Description Least significant byte of SCL low timeout value that determines the timeout period of SCL low. 18.4 Functional description This section provides a comprehensive functional description of the I2C module. 18.4.
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Chapter 18 Inter-Integrated Circuit (I2C) M SB SCL SDA 1 SDA Start Signal 3 4 5 6 7 8 9 A D 7 A D 6 A D 5 A D 4 A D 3 A D 2 A D 1 R /W C a llin g A d d re s s Start Signal SCL M SB LSB 2 3 4 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 D a ta B y te 5 6 7 8 A D 7 A D 6 A D 5 A D 4 A D 3 A D 2 A D 1 R /W C a llin g A d d re s s 1 9 R e a d / Ack W rite Bit XX 9 No Stop Ack Signal Bit M SB LSB 2 2 R e a d / Ack W rite Bit M SB 1 XXX LSB 1 LSB 2 3 4 5 6 7 8 9
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Functional description No two slaves in the system can have the same address. If the I2C module is the master, it must not transmit an address that is equal to its own slave address. The I2C module cannot be master and slave at the same time. However, if arbitration is lost during an address cycle, the I2C module reverts to slave mode and operates correctly even if it is being addressed by another master. 18.4.1.
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Chapter 18 Inter-Integrated Circuit (I2C) 18.4.1.5 Repeated START signal The master may generate a START signal followed by a calling command without generating a STOP signal first. This action is called a repeated START. The master uses a repeated START to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. 18.4.1.6 Arbitration procedure The I2C bus is a true multimaster bus that allows more than one master to be connected on it.
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Functional description D e la y S ta rt C o u n tin g H ig h P e rio d SCL1 SCL2 SCL In te rn a l C o u n te r R e s e t Figure 18-15. I2C clock synchronization 18.4.1.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfers. A slave device may hold SCL low after completing a single byte transfer (9 bits). In this case, it halts the bus clock and forces the master clock into wait states until the slave releases SCL. 18.4.1.
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Chapter 18 Inter-Integrated Circuit (I2C) Table 18-15.
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Functional description 18.4.2 10-bit address For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte. Various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. 18.4.2.1 Master-transmitter addresses a slave-receiver The transfer direction is not changed.
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Chapter 18 Inter-Integrated Circuit (I2C) After a repeated START condition (Sr), all other slave devices also compare the first seven bits of the first byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them are addressed because R/W = 1 (for 10-bit devices), or the 11110XX slave address (for 7-bit devices) does not match. Table 18-17.
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Functional description 18.4.4 System management bus specification SMBus provides a control bus for system and power management related tasks. A system can use SMBus to pass messages to and from devices instead of tripping individual control lines. Removing the individual control lines reduces pin count. Accepting messages ensures future expandability.
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Chapter 18 Inter-Integrated Circuit (I2C) A HIGH timeout occurs after a START condition appears on the bus but before a STOP condition appears on the bus. Any master detecting this scenario can assume the bus is free when either of the following occurs: • SHTF1 rises. • The BUSY bit is high and SHTF1 is high. When the SMBDAT signal is low and the SMBCLK signal is high for a period of time, another kind of timeout occurs. The time period must be defined in software.
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Functional description 18.4.4.2 FAST ACK and NACK To improve reliability and communication robustness, implementation of packet error checking (PEC) by SMBus devices is optional for SMBus devices but required for devices participating in and only during the address resolution protocol (ARP) process. The PEC is a CRC-8 error checking byte, calculated on all the message bytes. The PEC is appended to the message by the device that supplied the last data byte.
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Chapter 18 Inter-Integrated Circuit (I2C) SMBus timeouts interrupt is driven by SLTF and masked with the IICIE bit. The SLTF bit must be cleared by software by writing 1 to it in the interrupt routine. You can determine the interrupt type by reading the Status Register. NOTE In master receive mode, the FACK bit must be set to zero before the last byte transfer. Table 18-18.
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Functional description 18.4.6.4 Arbitration lost interrupt The I2C is a true multimaster bus that allows more than one master to be connected on it. If two or more masters try to control the bus at the same time, the relative priority of the contending masters is determined by a data arbitration procedure. The I2C module asserts the arbitration-lost interrupt when it loses the data arbitration process and the ARBL bit in the Status Register is set. Arbitration is lost in the following circumstances: 1.
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Chapter 18 Inter-Integrated Circuit (I2C) occurs within the number of clock cycles programmed in this register is ignored by the I2C module. The programmer must specify the size of the glitch (in terms of bus clock cycles) for the filter to absorb and not pass. Noise suppress circuits SCL, SDA internal signals SCL, SDA external signals DFF DFF DFF DFF Figure 18-17. Programmable input glitch filter diagram 18.4.
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Initialization/application information 2. 3. 4. 5. • to enable or disable general call • to select 10-bit or 7-bit addressing mode Write: Address Register 1 to set the slave address Write: Control Register 1 to enable the I2C module and interrupts Initialize RAM variables (IICEN = 1 and IICIE = 1) for transmit data Initialize RAM variables used to achieve the routine shown in the following figure Module Initialization (Master) 1.
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Chapter 18 Inter-Integrated Circuit (I2C) Clear IICIF Y Tx Master mode? N Rx Y Tx/Rx? Last byte transmitted? Y Arbitration lost? N Clear ARBL N N Last byte to be read? RXAK=0? N End of address cycle (master Rx)? Y Y (read) 2nd to last byte to be read? Write next byte to Data reg Set TXACK Address transfer see note 1 N Data transfer see note 2 Tx/Rx? Tx Y Generate stop signal (MST=0) IIAAS=1? Rx SRW=1? N (write) N N Y IIAAS=1? Y N Y Y Y Set TX mode ACK from receiver? N W
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Initialization/application information Y N SLTF or SHTF2=1? N FACK=1? See typical I2C interrupt routine flow chart Y Clear IICIF Y Tx Master mode? N Rx Y Tx/Rx? Last byte transmitted? Y Last byte to be read? Y N RXAK=0? 2nd to last byte to be read? N N Y N Clear IICIF Y (read) Delay (note 2) Read data and Soft CRC Set TXAK to proper value Delay (note 2) Set TXACK=1 Clear FACK=0 Write next byte to Data reg Switch to Rx mode Generate stop signal (MST=0) Y IAAS=1? Y Delay (note 2
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Chapter 19 Analog-to-digital converter (ADC) 19.1 Introduction The 12-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. 19.1.
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External Signal Description 19.1.2 Block Diagram This figure provides a block diagram of the ADC module.
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Chapter 19 Analog-to-digital converter (ADC) Table 19-1. Signal Properties Name Function AD23–AD0 Analog Channel inputs VREFH High reference voltage VREFL Low reference voltage VDDA Analog power supply VSSA Analog ground 19.2.1 Analog Power (VDDA) The ADC analog portion uses VDDA as its power connection. In some packages, VDDA is connected internally to VDD. If externally available, connect the VDDA pin to the same voltage potential as VDD.
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ADC Control Registers 19.2.5 Analog Channel Inputs (ADx) The ADC module supports up to 24 separate analog inputs. An input is selected for conversion through the ADCH channel select bits. 19.3 ADC Control Registers ADC memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 10 Status and Control Register 1 (ADC_SC1) 8 R/W 1Fh 19.3.1/526 11 Status and Control Register 2 (ADC_SC2) 8 R/W 08h 19.3.
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Chapter 19 Analog-to-digital converter (ADC) ADC_SC1 field descriptions Field 7 COCO Description Conversion Complete Flag Conversion Complete Flag. The COCO flag is a read-only bit set each time a conversion is completed when the compare function is disabled (ADC_SC2[ACFE] = 0). When the compare function is enabled (ADC_SC2[ACFE] = 1), the COCO flag is set upon completion of a conversion only if the compare result is true.
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ADC Control Registers 19.3.2 Status and Control Register 2 (ADC_SC2) The ADC_SC2 register controls the compare function, conversion trigger, and conversion active of the ADC module. Address: 10h base + 1h offset = 11h Bit Read 7 Write Reset 6 ADACT 0 5 4 ADTRG ACFE ACFGT 0 0 0 3 2 FEMPTY FFULL 1 0 1 0 0 0 0 ADC_SC2 field descriptions Field 7 ADACT Description Conversion Active Indicates that a conversion is in progress.
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Chapter 19 Analog-to-digital converter (ADC) ADC_SC2 field descriptions (continued) Field Description 0 1 1–0 Reserved Indicates that ADC result FIFO is not full and next conversion data still can be stored into FIFO. Indicates that ADC result FIFO is full and next conversion will override old data in case of no read action. This field is reserved. This read-only field is reserved and always has the value 0. 19.3.
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ADC Control Registers ADC_SC3 field descriptions (continued) Field Description 00 01 10 11 1–0 ADICLK 8-bit conversion (N=8) 10-bit conversion (N=10) 12-bit conversion (N=12) Reserved Input Clock Select ADICLK bits select the input clock source to generate the internal clock ADCK. 00 01 10 11 Bus clock Bus clock divided by 2 Alternate clock (ALTCLK) Asynchronous clock (ADACK) 19.3.
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Chapter 19 Analog-to-digital converter (ADC) ADC_SC4 field descriptions (continued) Field 2–0 AFDEP Description FIFO Depth enables the FIFO function and sets the depth of FIFO. When AFDEP is cleared, the FIFO is disabled. When AFDEP is set to nonzero, the FIFO function is enabled and the depth is indicated by the AFDEP bits. The ADCH in ADCSC1 and ADCRH:ADCRL must be accessed by FIFO mode when FIFO function is enabled.
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ADC Control Registers ADC_RH field descriptions Field 7–0 ADR Description Conversion Result[15:8] 19.3.6 Conversion Result Low Register (ADC_RL) ADC_RL contains the lower eight bits of the result of a 12-bit conversion. This register is updated each time a conversion completes except when automatic compare is enabled and the compare condition is not met. In 12-bit mode, reading ADC_RH prevents the ADC from transferring subsequent conversion results into the result registers until ADC_RL is read.
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Chapter 19 Analog-to-digital converter (ADC) 19.3.7 Compare Value High Register (ADC_CVH) In 12-bit mode, this register holds the upper four bits of the 12-bit compare value. These bits are compared to the upper four bits of the result following a conversion in 12-bit mode when the compare function is enabled. Address: 10h base + 6h offset = 16h Bit Read Write Reset 7 6 5 4 3 2 1 0 0 0 0 0 CV 0 0 0 0 ADC_CVH field descriptions Field 7–0 CV Description Conversion Result[15:8] 19.3.
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ADC Control Registers 19.3.9 Pin Control 1 Register (ADC_APCTL1) The pin control registers disable the I/O port control of MCU pins used as analog inputs. APCTL1 is used to control the pins associated with channels 0-7 of the ADC module.
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Chapter 19 Analog-to-digital converter (ADC) ADC_APCTL1 field descriptions (continued) Field 1 ADPC1 Description ADC Pin Control 1 ADPC1 controls the pin associated with channel AD1. 0 1 0 ADPC0 AD1 pin I/O control enabled. AD1 pin I/O control disabled. ADC Pin Control 0 ADPC0 controls the pin associated with channel AD0. 0 1 AD0 pin I/O control enabled. AD0 pin I/O control disabled. 19.3.10 Pin Control 2 Register (ADC_APCTL2) APCTL2 controls channels 8-15 of the ADC module.
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Functional description ADC_APCTL2 field descriptions (continued) Field Description 0 1 3 ADPC11 ADC Pin Control 11 ADPC11 controls the pin associated with channel AD11. 0 1 2 ADPC10 ADPC10 controls the pin associated with channel AD10. AD10 pin I/O control enabled. AD10 pin I/O control disabled. ADC Pin Control 9 ADPC9 controls the pin associated with channel AD1. 0 1 0 ADPC8 AD11 pin I/O control enabled. AD11 pin I/O control disabled. ADC Pin Control 10 0 1 1 ADPC9 AD12 pin I/O control enabled.
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Chapter 19 Analog-to-digital converter (ADC) The ADC module has the capability of automatically comparing the result of a conversion with the contents of its compare registers. The compare function is enabled by setting the ADC_SC2[ACFE] bit and operates with any of the conversion modes and configurations. 19.4.1 Clock select and divide control One of four clock sources can be selected as the clock source for the ADC module.
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Functional description • The input buffer is disabled. A read of the I/O port returns a zero for any pin with its input buffer disabled. • The pullup is disabled. 19.4.3 Hardware trigger The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT, that is enabled when the ADC_SC2[ADTRG] bit is set. This source is not available on all MCUs. See the module introduction for information on the ADHWT source specific to this MCU.
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Chapter 19 Analog-to-digital converter (ADC) If continuous conversions are enabled, a new conversion is automatically initiated after the completion of the current conversion. In software triggered operation, continuous conversions begin after ADC_SC1 is written and continue until aborted. In hardware triggered operation, continuous conversions begin after a hardware trigger event and continue until aborted. 19.4.4.
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Functional description • A write to ADC_SC2, ADC_SC3, ADC_SC4, ADC_CVH, or ADC_CVL occurs. This indicates a mode of operation change has occurred and the current and rest of conversions (when ADC_SC4[AFDEP] are not all 0s) are therefore invalid. • The MCU is reset. • The MCU enters stop mode with ADACK not enabled. When a conversion is aborted, the contents of the data registers, ADC_RH and ADC_RL, are not altered.
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Chapter 19 Analog-to-digital converter (ADC) Table 19-13. Total conversion time vs.
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Functional description 19.4.5 Automatic compare function The compare function can be configured to check for an upper or lower limit. After the input is sampled and converted, the result is added to the two's complement of the compare value (ADC_CVH and ADC_CVL). When comparing to an upper limit (ADC_SC2[ACFGT] = 1), if the result is greater-than or equal-to the compare value, ADC_SC1[COCO] is set.
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Chapter 19 Analog-to-digital converter (ADC) the ADC_SC4[AFDEP] bits, no matter whether software or hardware trigger is set. Read ADC_SC1[ADCH] will read the current active channel value. Write to ADC_SC1[ADCH] will re-fill channel FIFO to initial new conversion. It will abort current conversion and any other conversions that did not start. Write to the ADC_SC1 after all the conversions are completed or ADC is in idle state.
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Functional description If software trigger is enabled, the next analog channel is fetched from analog input channel FIFO as soon as a conversion completes and its result is stored in the result FIFO. When all conversions set in the analog input channel FIFO completes, the ADC_SC1[COCO] bit is set and an interrupt request will be submitted to CPU if the ADC_SC1[AIEN] bit is set.
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Chapter 19 Analog-to-digital converter (ADC) th The n AD channel fetch max = AFDEP Channel FIFO fulfilled Start FIFOed Conversion n 0 max COCO = 1 Conversions Completed The nth AD result store The nth AD channel fetch Software Triggered Single Conversion max = AFDEP Channel FIFO fulfilled Start FIFOed Conversion n 0 max 0 n max ADC_SC1[COCO] = 1 Conversions Completed The nth AD result store The nth AD channel fetch when n hardware trigger occurs 0 n max Software Triggered Continuous
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Functional description 19.4.7 MCU wait mode operation Wait mode is a low-power consumption standby mode from which recovery is fast because the clock sources remain active. If a conversion is in progress when the MCU enters wait mode, it continues until completion. Conversions can be initiated while the MCU is in wait mode by means of the hardware trigger or if continuous conversions are enabled.
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Chapter 19 Analog-to-digital converter (ADC) A conversion complete event sets the ADC_SC1[COCO] and generates an ADC interrupt to wake the MCU from stop3 mode if the ADC interrupt is enabled (ADC_SC1[AIEN] = 1). In fifo mode, ADC cannot complete the conversion operation fully or wake the MCU from stop3 mode. Note The ADC module can wake the system from low-power stop and cause the MCU to begin consuming run-level currents without generating a system level interrupt.
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Initialization information 3. Update status and control register 1 (ADC_SC1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. The input channel on which conversions will be performed is also selected here. 19.5.1.
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Chapter 19 Analog-to-digital converter (ADC) 19.5.2.1 Pseudo-code example In this example, the ADC module is set up with interrupts enabled to perform a single hardware triggered 10-bit 4-level-FIFO conversion at low power with a long sample time on input channels of 1, 3, 5, and 7. Here the internal ADCK clock is derived from the bus clock divided by 1. Example: 19.5.2.1.
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Application information 19.6 Application information This section contains information for using the ADC module in applications. The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an A/D converter. 19.6.1 External pins and routing The following sections discuss the external pins associated with the ADC module and how they are used for best results. 19.6.1.
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Chapter 19 Analog-to-digital converter (ADC) When available on a separate pin, VREFH may be connected to the same potential as VDDA, or may be driven by an external source between the minimum VDDA spec and the VDDA potential (VREFH must never exceed VDDA). When available on a separate pin, VREFL must be connected to the same voltage potential as VSSA. VREFH and VREFL must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package.
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Application information For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be transitioning during conversions. 19.6.2 Sources of error Several sources of error exist for A/D conversions. These are discussed in the following sections. 19.6.2.1 Sampling error For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the maximum input resistance of approximately 7 kΩ and input capacitance of approximately 5.
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Chapter 19 Analog-to-digital converter (ADC) • If inductive isolation is used from the primary supply, an additional 1 µF capacitor is placed from VDDA to VSSA. • VSSA (and VREFL, if connected) is connected to VSS at a quiet point in the ground plane. • Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or immediately after initiating (hardware or software triggered conversions) the ADC conversion.
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Application information There is an inherent quantization error due to the digitization of the result. For 8-bit or 10-bit conversions the code transitions when the voltage is at the midpoint between the points where the straight line transfer function is exactly represented by the actual transfer function. Therefore, the quantization error will be ± 1/2 lsb in 8- or 10-bit mode.
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Chapter 19 Analog-to-digital converter (ADC) 19.6.2.6 Code jitter, non-monotonicity, and missing codes Analog-to-digital converters are susceptible to three special forms of error. These are code jitter, non-monotonicity, and missing codes. Code jitter occurs when, at certain points, a given input voltage converts to one of two values when sampled repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the converter yields the lower code (and vice-versa).
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Application information MC9S08PA60 Reference Manual, Rev. 1, 9/2012 556 Freescale Semiconductor, Inc.
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Chapter 20 Analog comparator (ACMP) 20.1 Introduction The analog comparator module (ACMP) provides a circuit for comparing two analog input voltages. The comparator circuit is designed to operate across the full range of the supply voltage (rail-to-rail operation). The analog mux provides a circuit for selecting an analog input signal from eight channels. One signal provided by the 6-bit DAC. The mux circuit is designed to operate across the full range of the supply voltage.
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Introduction 20.1.2 Modes of operation This section defines the ACMP operation in wait, stop, and background debug modes. 20.1.2.1 Operation in wait mode The ACMP continues to operate in wait mode if enabled. The interrupt can wake the MCU if enabled. 20.1.2.2 Operation in stop mode The ACMP (including DAC and CMP) continues to operate in stop3 mode if enabled. If ACIEN is set, a ACMP interrupt can be generated to wake the MCU up from stop3 mode.
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Chapter 20 Analog comparator (ACMP) DACREF MUX VDDA Bandgap 6-bit DAC DACEN ACE ACOPE MUX DACVAL ACPSEL ACNSEL + External Output – MUX ACMP0 ACMP1 ACMP2 Interrupt Edge Control Logic HYST ACO ACMOD ACF ACIE Note: ACMP2 is reserved for internal test only. Figure 20-1. ACMP block diagram 20.2 External signal description The output of ACMP can also be mapped to an external pin.
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Memory map and register definition 20.3.1 ACMP Control and Status Register (ACMP_CS) Address: 2Ch base + 0h offset = 2Ch Bit Read Write Reset 7 6 5 4 ACE HYST ACF ACIE 0 0 0 0 3 ACO 0 2 1 ACOPE 0 ACMOD 0 0 0 ACMP_CS field descriptions Field 7 ACE Description Analog Comparator Enable This bit enables the ACMP module. 0 1 6 HYST The ACMP is disabled. The ACMP is enabled. Analoy Comparator Hystersis Selection This bit is used to select ACMP hystersis. 0 1 20 mV. 30 mV.
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Chapter 20 Analog comparator (ACMP) ACMP_CS field descriptions (continued) Field Description 10 11 ACMP interrupt on output falling edge. ACMP interrupt on output falling or rising edge. 20.3.2 ACMP Control Register 0 (ACMP_C0) Address: 2Ch base + 1h offset = 2Dh Bit Read Write Reset 7 6 5 0 4 3 2 0 ACPSEL 0 0 0 1 0 0 0 ACNSEL 0 0 0 2 1 0 0 0 0 ACMP_C0 field descriptions Field Description 7–6 Reserved This field is reserved.
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Functional description ACMP_C1 field descriptions Field 7 DACEN Description DAC Enable The DACEN bit enables the output of 6-bit DAC. 0 1 The DAC is disabled. The DAC is enabled. 6 DACREF DAC Reference Select 5–0 DACVAL DAC Output Level Selection 0 1 The DAC selects Bandgap as the reference. The DAC selects VDDA as the reference. Select the output voltage using the given formula: Voutput= (Vin/64)x(DACVAL[5:0]+1) The Voutput range is from Vin/64 to Vin, the step is Vin/64 20.3.
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Chapter 20 Analog comparator (ACMP) data set in ACMP_C1[DACVAL] bits to a stepped analog output, which is fed into ACMP as an internal reference input. This stepped analog output is also mapped out of the module. The output voltage range is from Vin/64 to Vin. The step size is Vin/64. The ACMP can achieve the analog comparison between positive input and negative input, and then give out a digital output and relevant interrupt.
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Resets Because the input-switching can cause problems on the ACMP inputs, the user should complete the input selection before enabling the ACMP and must not change the input selection setting when the ACMP is enabled to avoid unexpected output. Similarly, because the DAC experiences a setup delay after the DACVAL is changed, the user should complete the setting of DACVAL before DAC is enabled. 20.6 Resets During a reset the ACMP is configured in the default mode. Both CMP and DAC are disabled. 20.
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Chapter 21 Cyclic redundancy check (CRC) 21.1 Introduction Cyclic redundancy check (CRC) generates 16/32-bit CRC code for error detection. The CRC can be configured to work as a standard CRC. It provides the user with programmable polynomial, SEED and other parameters required to implement a 16-bit or 32-bit CRC standard. These parameters are detailed in further sections. 21.
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Modes of operation TOT Reverse Logic FXOR TOTR NOT Logic Reverse Logic Seed MUX CRC_D0 CRC_D1 CRC_D2 CRC_D3 WAS CRC Data CRC_D0 CRC_D1 CRC_D2 CRC_D3 Checksum CRC Engine CRC_P0 CRC_P1 CRC_P2 CRC_P3 Data Combine Logic Polynomial 16-/32-bit Select TCRC Figure 21-1. Cyclic redundancy check (S08CRC) block diagram 21.4 Modes of operation This section defines the CRC operation in run, wait, and stop modes. • Run mode - This is the basic mode of operation in which CRC is full functional.
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Chapter 21 Cyclic redundancy check (CRC) 21.5.1 CRC Data 0 Register (CRC_D0) D0 is one of the CRC data registers (D0:D3). The set of CRC data registers contains the value of seed, data, and checksum. When CRC_CTRL[WAS] bit is set, any write to the data registers is regarded as seed for CRC module.
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Register definition CRC_D1 field descriptions Field 7–0 D1 Description CRC Data Bit 23:16 21.5.3 CRC Data 2 Register (CRC_D2) D2 is one of the CRC data registers (D0:D3). The set of CRC data registers contains the value of seed, data, and checksum. When CRC_CTRL[WAS] bit is set, any write to the data registers is regarded as seed for CRC module.
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Chapter 21 Cyclic redundancy check (CRC) 21.5.4 CRC Data 3 Register (CRC_D3) D3 is one of the CRC data registers (D0:D3). The set of CRC data registers contains the value of seed, data, and checksum. When CRC_CTRL[WAS] bit is set, any write to the data registers is regarded as seed for CRC module.
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Register definition 21.5.6 CRC Polynomial 1 Register (CRC_P1) P1 is one of the CRC polynomial registers (P0:P3). The set of CRC polynominal registers contains the value of polynomial. The registers of P0:P1 contain the MSB 16-bit of CRC polynomial, which is used only in CRC 32-bit mode. The registers of P2:P3 contain the LSB 16-bit of CRC polynomial, which is used in both CRC 16- and 32-bit modes.
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Chapter 21 Cyclic redundancy check (CRC) 21.5.8 CRC Polynomial 3 Register (CRC_P3) P3 is one of the CRC polynomial registers (P0:P3). The set of CRC polynominal registers contains the value of polynomial. The registers of P0:P1 contain the MSB 16-bit of CRC polynomial, which is used only in CRC 32-bit mode. The registers of P2:P3 contain the LSB 16-bit of CRC polynomial, which is used in both CRC 16- and 32-bit modes.
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Functional description CRC_CTRL field descriptions (continued) Field 3 Reserved 2 FXOR Description This field is reserved. This read-only field is reserved and always has the value 0. Complement of Read This bit allows CRC module to output the complement of the final CRC checksum. 0 1 1 WAS Write CRC data register as seed This bit indicates the data written to the CRC data register (D0:D3) is seed or data. 0 1 0 TCRC Normal checksum output. Complement of checksum output.
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Chapter 21 Cyclic redundancy check (CRC) 2. Optional to enable reverse and complement function. Please see Bit reverse and Result complement for details. 3. Write 32-bit polynomial to CRC_P0:CRC_P3. 4. Set CRC_CTRL[WAS] bit to allow CRC_D0:CRC_D3 written by seed. 5. Write 32-bit seed to CRC_D0:CRC_D3. 6. Clear CRC_CTRL[WAS] bit to start 32-bit CRC calculation. 7. Dummy CRC_D3 with 8-bit CRC raw data. 8. Get the checksum from CRC_D0:CRC_D3 when all CRC raw data dummied. 21.6.
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Functional description CRC_CTRL CRC_P2P3 CRC_D2D3 CRC_CTRL = = = = CRC_CTRL_WAS_MASK; // 16-bit CRC, ready to dummy seed 0x1021; // Standard CCITT polynomail of (x^16 + x^12 + x^5 + 1) 0xFFFF; // Set seed by 0xFFFF 0x00; for ( i = 0 ; i < 128 ; i++ ) { CRC_D3 = 'A'; // Dummy 256 `A' CRC_D3 = 'A'; } // Get 0xea0b in CRC_D2:CRC_D3 here MC9S08PA60 Reference Manual, Rev. 1, 9/2012 574 Freescale Semiconductor, Inc.
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Chapter 22 Watchdog (WDOG) 22.1 Introduction The watchdog timer (WDOG) module is an independent timer that is available for system use. It provides a safety feature to ensure that software is executing as planned and that the CPU is not stuck in an infinite loop or executing unintended code. If the WDOG module is not serviced (refreshed) within a certain period, it resets the MCU. 22.1.
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Introduction • Provides robust check that program flow is faster than expected • Early refresh attempts trigger a reset • Optional timeout interrupt to allow post-processing diagnostics • Interrupt request to CPU with interrupt vector for an interrupt service routine (ISR) • Forced reset occurs 128 bus clocks after the interrupt vector fetch • Configuration bits are write-once-after-reset to ensure watchdog configuration cannot be mistakenly altered • Robust write sequence for unlocking write-once configur
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Chapter 22 Watchdog (WDOG) 22.2 Memory map and register definition WDOG memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 3030 Watchdog Control and Status Register 1 (WDOG_CS1) 8 R/W 80h 22.2.1/577 3031 Watchdog Control and Status Register 2 (WDOG_CS2) 8 R/W 01h 22.2.2/579 3032 Watchdog Counter Register: High (WDOG_CNTH) 8 R 00h 22.2.3/580 3033 Watchdog Counter Register: Low (WDOG_CNTL) 8 R 00h 22.2.
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Memory map and register definition WDOG_CS1 field descriptions (continued) Field Description 0 1 5 UPDATE Allow updates This write-once bit allows software to reconfigure the watchdog without a reset. 0 1 4–3 TST Watchdog interrupts are disabled. Watchdog resets are not delayed. Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks. Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. Updates allowed.
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Chapter 22 Watchdog (WDOG) 22.2.2 Watchdog Control and Status Register 2 (WDOG_CS2) This section describes the function of the watchdog control and status register 2. Address: 3030h base + 1h offset = 3031h Bit Read Write Reset 7 WIN 6 5 FLG 0 w1c 0 0 0 4 3 2 1 0 PRES 0 0 0 CLK 0 0 1 WDOG_CS2 field descriptions Field 7 WIN Description Watchdog Window This write-once bit enables window mode. See the "Window mode" section.
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Memory map and register definition 22.2.3 Watchdog Counter Register: High (WDOG_CNTH) This section describes the watchdog counter registers: high (CNTH) and low (CNTL) combined. The watchdog counter registers CNTH:L provide access to the value of the free running watchdog counter. Software can read the counter registers at any time. Software cannot write directly to the watchdog counter; however, two write sequences to these registers have special functions: 1.
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Chapter 22 Watchdog (WDOG) WDOG_CNTL field descriptions Field 7–0 CNTLOW Description Low byte of the Watchdog Counter 22.2.5 Watchdog Timeout Value Register: High (WDOG_TOVALH) This section describes the watchdog timeout value registers: high (TOVALH) and low (TOVALL) combined. TOVALH:L contains the 16-bit value used to set the timeout period of the watchdog. The watchdog counter (CNTH:L) is continuously compared with the timeout value (TOVALH:L).
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Memory map and register definition WDOG_TOVALL field descriptions Field 7–0 TOVALLOW Description Low byte of the timeout value 22.2.7 Watchdog Window Register: High (WDOG_WINH) This section describes the watchdog window registers: high (WINH) and low (WINL) combined. When window mode is enabled (WDOG_CS2[WIN] bit is set), WDOG_WINH:L determines the earliest time that a refresh sequence is considered valid. See the "Watchdog refresh mechanism" section. WDOG_WINH:L must be less than WDOG_TOVALH:L.
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Chapter 22 Watchdog (WDOG) 22.3 Functional description The WDOG module provides a fail safe mechanism to ensure the system can be reset to a known state of operation in case of system failure, such as the CPU clock stopping or there being a run away condition in the software code. The watchdog counter runs continuously off a selectable clock source and expects to be serviced (refreshed) periodically. If it is not, it resets the system.
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Functional description WDOG counter WDOG_TOVALH:L WDOG_WINH:L Refresh opportunity in window mode 0 Refresh opportunity (not in window mode) Time Figure 22-10. Refresh opportunity for the Watchdog counter 22.3.1.1 Window mode Software finishing its main control loop faster than expected could be an indication of a problem. Depending on the requirements of the application, the WDOG can be programmed to force a reset when refresh attempts are early.
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Chapter 22 Watchdog (WDOG) Note Before starting the refresh sequence, disable global interrupts. Otherwise, an interrupt could effectively invalidate the refresh sequence if writing the four bytes takes more than 16 bus clocks. Re-enable interrupts when the sequence is finished. 22.3.1.3 Example code: Refreshing the Watchdog The following code segment shows the refresh write sequence of the WDOG module. /* Refresh watchdog */ for (;;) // main loop { ...
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Functional description 22.3.2.1 Reconfiguring the Watchdog In some cases (such as when supporting a bootloader function), users may want to reconfigure or disable the watchdog without forcing a reset first. By setting the WDOG_CS1[UPDATE] bit to a 1 on the initial configuration of the watchdog after a reset, users can reconfigure the watchdog at any time by executing an unlock sequence. (Conversely, if the WDOG_CS1[UPDATE] remains 0, the only way to reconfigure the watchdog is by initiating a reset.
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Chapter 22 Watchdog (WDOG) 22.3.3 Clock source The watchdog counter has four clock source options selected by programming the WDOG_CS2[CLK] bits: • bus clock • internal Low Power Oscillator (LPO) running at approximately 1 kHz (This is the default source.) • internal 32 kHz clock • external clock The options allow software to select a clock source independent of the bus clock for applications that need to meet more robust safety requirements.
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Functional description 22.3.4 Using interrupts to delay resets When interrupts are enabled (WDOG_CS1[INT] = 1), the watchdog first generates an interrupt request upon a reset triggering event (such as a counter timeout or invalid refresh attempt). The watchdog delays forcing a reset for 128 bus clocks to allow the interrupt service routine (ISR) to perform tasks, such as analyzing the stack to debug code. When interrupts are disabled (WDOG_CS1[INT] = 0), the watchdog does not delay forcing a reset. 22.3.
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Chapter 22 Watchdog (WDOG) For active background mode and stop3 mode, in addition to the above configurations, a clock source other than the bus clock must be used as the reference clock for the counter; otherwise, the watchdog cannot function. 22.3.7 Fast testing of the watchdog Before executing application code in safety critical applications, users are required to test that the watchdog works as expected and resets the MCU.
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Functional description 6. Confirm the WDOG_CS1[TST] field shows a test (10b or 11b) was performed. If confirmed, the count and compare functions work for the selected byte. Repeat the procedure, selecting the other byte in Step 2. NOTE The WDOG_CS1[TST] bits are cleared by a POR reset only and not affected by other resets. 22.3.7.
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Chapter 23 Development support 23.1 Introduction This chapter describes the single-wire background debug mode (BDM), which uses the on-chip background debug controller (BDC) module, and the independent on-chip realtime in-circuit emulation (ICE) system, which uses the on-chip debug (DBG) module. 23.1.1 Forcing active background The method for forcing active background mode depends on the specific HCS08 derivative.
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Background debug controller (BDC) • BDC clock runs in stop mode, if BDC enabled • Watchdog disabled by default while in active background mode.
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Chapter 23 Development support Typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire background debug system. Depending on the development tool vendor, this interface pod may use a standard RS-232 serial port, a parallel printer port, or some other type of communications such as a universal serial bus (USB) to communicate between the host PC and the pod.
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Background debug controller (BDC) BKGD is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required. Unlike typical open-drain pins, the external RC time constant on this pin, which is influenced by external capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts. Refer to Communication details for more detail.
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Chapter 23 Development support host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal during this period.
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Background debug controller (BDC) The following figure shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target HCS08 finishes it.
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Chapter 23 Development support Commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most significant bit first) / =separates parts of the command d=delay 16 target BDC clock cycles AAAA = a 16-bit address in the host-to-target direction RD = 8 bits of read data in the target-to-host direction WD = 8 bits of write data in the host-to-target direction RD16 = 16 bits of read data in the target-to-host direction WD16 = 16 bits of write data in the host-to-target direction SS =
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Background debug controller (BDC) Table 23-1.
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Chapter 23 Development support The target, upon detecting the SYNC request from the host (which is a much longer low time than would ever occur during normal BDC communications): • Waits for BKGD to return to a logic high • Delays 16 cycles to allow the host to stop driving the high speedup pulse • Drives BKGD low for 128 BDC clock cycles • Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD • Removes all drive to the BKGD pin so it reverts to high impedance The host measures the low time
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On-chip debug system (DBG) and a flexible trigger system to decide when to capture bus information and what information to capture. The system relies on the single-wire background debug system to access debug control registers and to read results out of the eight stage FIFO. The debug module includes control and status registers that are accessible in the user's memory map. These registers are located in the high register space to avoid using valuable direct page memory space.
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Chapter 23 Development support 23.3.2 Bus capture information and FIFO operation The usual way to use the FIFO is to setup the trigger mode and other control options, then arm the debugger. When the FIFO has filled or the debugger has stopped storing data into the FIFO, you would read the information out of it in the order it was stored into the FIFO. Status bits indicate the number of words of valid information that are in the FIFO as data is stored into it.
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On-chip debug system (DBG) 23.3.3 Change-of-flow information To minimize the amount of information stored in the FIFO, only information related to instructions that cause a change to the normal sequential execution of instructions is stored. With knowledge of the source and object code program stored in the target system, an external debugger system can reconstruct the path of execution through many instructions from the change-of-flow information stored in the FIFO.
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Chapter 23 Development support 23.3.5 Trigger modes The trigger mode controls the overall behavior of a debug run. The 4-bit TRG field in the DBGT register selects one of nine trigger modes. When TRGSEL = 1 in the DBGT register, the output of the comparator must propagate through an opcode tracking circuit before triggering FIFO actions.
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On-chip debug system (DBG) A AND B Data (Full Mode) ̶ This is called a full mode because address, data, and R/W (optionally) must match within the same bus cycle to cause a trigger event. Comparator A checks address, the low byte of comparator B checks data, and R/W is checked against RWA if RWAEN = 1. The high-order half of comparator B is not used.
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Chapter 23 Development support the end of the pipe, the CPU executes a BGND instruction to go to active background mode rather than executing the tagged opcode. A force-type breakpoint causes the CPU to finish the current instruction and then go to active background mode. If the background mode has not been enabled (ENBDM = 1) by a serial WRITE_CONTROL command through the BKGD pin, the CPU will execute an SWI instruction instead of going to active background mode. 23.
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Memory map and register description Address: 0h base + 0h offset = 0h Bit Read Write Reset 7 6 ENBDM 0 5 BDMACT 4 3 BKPTEN FTS CLKSW 0 0 0 0 2 1 0 WS WSF DVF 0 0 0 BDC_SCR field descriptions Field 7 ENBDM Description Enable BDM (Permit Active Background Mode) Typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal reset clears it.
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Chapter 23 Development support BDC_SCR field descriptions (continued) Field Description 0 1 1 WSF Wait or Stop Failure Status This status bit is set if a memory access command failed due to the target CPU executing a wait or stop instruction at or about the same time. The usual recovery strategy is to issue a BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command that failed, then return to the user program.
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Memory map and register description 23.4.3 BDC Breakpoint Register: Low (BDC_BKPTL) BDC_BKPTH and BDC_BKPTL registers hold the address for the hardware breakpoint in the BDC. The BDC_SCR[FTS] and BDC_SCR[BKPTEN] bits are used to enable and configure the breakpoint logic. Dedicated serial BDC commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDC_BKPTH and BDC_BKPTL register.
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Chapter 23 Development support BDC_SBDFR field descriptions (continued) Field Description A serial active background mode command such as WRITE_BYTE allows an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. MC9S08PA60 Reference Manual, Rev. 1, 9/2012 Freescale Semiconductor, Inc.
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Memory map and register description MC9S08PA60 Reference Manual, Rev. 1, 9/2012 610 Freescale Semiconductor, Inc.
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Chapter 24 Debug module (DBG) 24.1 Introduction The DBG module implements an on-chip ICE (in-circuit emulation) system and allows non-intrusive debug of application software by providing an on-chip trace buffer with flexible triggering capability. The trigger also can provide extended breakpoint capacity. The on-chip ICE system is optimized for the S08CPUV6 8-bit architecture and supports 2 M bytes of memory space. 24.1.
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Introduction • FIFO for storing change of flow information and event only data • Source address of conditional branches taken • Destination address of indirect JMP and JSR instruction • Destination address of interrupts, RTI, RTC, and RTS instruction • Data associated with Event B trigger modes • Ability to End-trace until reset and begin-trace from reset 24.1.2 Modes of operation The on-chip ICE system can be enabled in all MCU functional modes. The DBG module is disabled if the MCU is secure.
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Chapter 24 Debug module (DBG) DBG Read Data Bus FIFO Data Address Bus[16:0] c o n t r o l Write Data Bus Read Data Bus Read/Write DBG Module Enable mmu_ppage_access1 Address/Data/Control Registers Trigger Break Control Logic match_A Comparator A match_B Comparator B Tag Force match_C Comparator C core_cof[1:0] control Change of Flow Indicators MCU in BDM MCU reset event only store Read DBGFL Read DBGFH Read DBGFX Instr.
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Memory map and registers DBG memory map Absolute address (hex) Width Access (in bits) Register name Reset value Section/ page 3010 Debug Comparator A High Register (DBG_CAH) 8 R/W FFh 24.3.1/614 3011 Debug Comparator A Low Register (DBG_CAL) 8 R/W FEh 24.3.2/615 3012 Debug Comparator B High Register (DBG_CBH) 8 R/W 00h 24.3.3/616 3013 Debug Comparator B Low Register (DBG_CBL) 8 R/W 00h 24.3.4/616 3014 Debug Comparator C High Register (DBG_CCH) 8 R/W 00h 24.3.
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Chapter 24 Debug module (DBG) DBG_CAH field descriptions Field 7–0 CA[15:8] Description Comparator A High Compare Bits The Comparator A High compare bits control whether Comparator A will compare the address bus bits [15:8] to a logic 1 or logic 0. 0 1 Compare corresponding address bit to a logic 0. Compare corresponding address bit to a logic 1. 24.3.2 Debug Comparator A Low Register (DBG_CAL) NOTE All the bits in this register reset to 1 in POR or non-end-run reset.
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Memory map and registers 24.3.3 Debug Comparator B High Register (DBG_CBH) NOTE All the bits in this register reset to 0 in POR or non-end-run reset. The bits are undefined in end-run reset. In the case of an end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits in this register do not change after reset.
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Chapter 24 Debug module (DBG) DBG_CBL field descriptions Field 7–0 CB[7:0] Description Comparator B Low The Comparator B Low compare bits control whether Comparator B will compare the address bus bits [7:0] to a logic 1 or logic 0. 0 1 Compare corresponding address bit to a logic 0. Compare corresponding address bit to a logic 1. 24.3.5 Debug Comparator C High Register (DBG_CCH) NOTE All the bits in this register reset to 0 in POR or non-end-run reset. The bits are undefined in end-run reset.
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Memory map and registers 24.3.6 Debug Comparator C Low Register (DBG_CCL) NOTE All the bits in this register reset to 0 in POR or non-end-run reset. The bits are undefined in end-run reset. In the case of an end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits in this register do not change after reset.
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Chapter 24 Debug module (DBG) DBG_FH field descriptions Field 7–0 F[15:8] Description FIFO High Data Bits The FIFO High data bits provide access to bits [15:8] of data in the FIFO. This register is not used in event only modes and will read a $00 for valid FIFO words. 24.3.8 Debug FIFO Low Register (DBG_FL) NOTE All the bits in this register reset to 0 in POR or non-end-run reset. The bits are undefined in end-run reset.
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Memory map and registers 24.3.9 Debug Comparator A Extension Register (DBG_CAX) NOTE All the bits in this register reset to 0 in POR or non-end-run reset. The bits are undefined in end-run reset. In the case of an end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits in this register do not change after reset.
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Chapter 24 Debug module (DBG) 24.3.10 Debug Comparator B Extension Register (DBG_CBX) NOTE All the bits in this register reset to 0 in POR or non-end-run reset. The bits are undefined in end-run reset. In the case of an end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits in this register do not change after reset.
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Memory map and registers 24.3.11 Debug Comparator C Extension Register (DBG_CCX) NOTE All the bits in this register reset to 0 in POR or non-end-run reset. The bits are undefined in end-run reset. In the case of an end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits in this register do not change after reset.
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Chapter 24 Debug module (DBG) 24.3.12 Debug FIFO Extended Information Register (DBG_FX) NOTE All the bits in this register reset to 0 in POR or non-end-run reset. The bits are undefined in end-run reset. In the case of an end-trace to reset where DBGEN = 1 and BEGIN = 0, the bits in this register do not change after reset.
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Memory map and registers DBG_C field descriptions Field 7 DBGEN Description DBG Module Enable Bit The DBGEN bit enables the DBG module. The DBGEN bit is forced to zero and cannot be set if the MCU is secure. 0 1 6 ARM Arm Bit The ARM bit controls whether the debugger is comparing and storing data in FIFO. 0 1 5 TAG The TAG bit controls whether a debugger or comparator C breakpoint will be requested as a tag or force breakpoint to the CPU. The TAG bit is not used if BRKEN = 0.
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Chapter 24 Debug module (DBG) NOTE The DBG trigger register (DBGT) can not be changed unless ARM=0. Address: 3010h base + Dh offset = 301Dh Bit Read Write Reset 7 6 TRGSEL BEGIN 0 1 5 4 3 2 0 0 1 0 0 0 TRG 0 0 0 DBG_T field descriptions Field 7 TRGSEL Description Trigger Selection Bit The TRGSEL bit controls the triggering condition for the comparators. 0 1 6 BEGIN Begin/End Trigger Bit The BEGIN bit controls whether the trigger begins or ends storing of data in FIFO.
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Memory map and registers 24.3.15 Debug Status Register (DBG_S) NOTE The figure shows the values in POR or non-end-run reset. The bits of AF, BF and CF are undefined and ARMF is reset to 0 in end-run reset. In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, ARMF gets cleared by reset but AF, BF, and CF do not change after reset.
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Chapter 24 Debug module (DBG) 24.3.16 Debug Count Status Register (DBG_CNT) NOTE All the bits in this register reset to 0 in POR or non-end-run reset. The bits are undefined in end-run reset. In the case of an end-trace to reset where DBGEN = 1 and BEGIN = 0, the CNT[3:0] bits do not change after reset.
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Functional description 24.4 Functional description This section provides a complete functional description of the on-chip ICE system. The DBG module is enabled by setting the DBG_C[DBGEN] bit. Enabling the module allows the arming, triggering and storing of data in the FIFO. The DBG module is made up of three main blocks, the comparators, trigger break control logic and the FIFO. 24.4.1 Comparator The DBG module contains three comparators, A, B, and C.
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Chapter 24 Debug module (DBG) When the DBG_C[ARM] and DBG_C[DBGEN] bits are set to one in loop1 capture mode, comparator C value registers are cleared to prevent the previous contents of these registers from interfering with the loop1 capture mode operation. When a COF event is detected, the address of the event is compared to the contents of the DBG_CCH and DBG_CCL registers to determine whether it is the same as the previous COF entry in the capture FIFO.
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Functional description breakpoints. To use comparators A and B as hardware breakpoints, set DBG_T = 0x81 for tag-type breakpoints and 0x01 for force-type breakpoints. This sets up an end-type trace with trigger mode "A OR B". Comparator C is not involved in the trigger logic for the on-chip ICE system. 24.4.3 Trigger selection The DBG_T[TRGSEL] bit is used to determine the triggering condition of the on-chip ICE system. DBG_T[TRGSEL] applies to both trigger A and B except in the event only trigger modes.
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Chapter 24 Debug module (DBG) trigger to the ICE logic to begin or end capturing information into the FIFO. In the case of an end-type (DBG_T[BEGIN] = 0) trace run, the qualified comparator signal stops the FIFO from capturing any more information. If a CPU breakpoint is also enabled, you would want DBG_C[TAG] and DBG_T[TRGSEL] to agree so that the CPU break occurs at the same place in the application program as the FIFO stopped capturing information.
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Functional description 24.4.4.3 Trigger modes The on-chip ICE system supports nine trigger modes. The trigger mode is used as a qualifier for either starting or ending the storing of data in the FIFO. When the match condition is met, the appropriate flag AF or BF is set in DBG_S register. Arming the DBG module clears the DBG_S[AF], DBG_S[BF], and DBG_S[CF] flags. In all trigger modes except for the event only modes change of flow addresses are stored in the FIFO.
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Chapter 24 Debug module (DBG) 24.4.4.3.6 A and B (full mode) In the A and B trigger mode, comparator A compares to the address bus and comparator B compares to the data bus. In the A and B trigger mode, if the match condition for A and B happen on the same bus cycle, both the DBG_S[AF] and DBG_S[BF] flags are set. If a match condition on only A or only B happens, no flags are set.
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Functional description The four control bits DBG_T[BEGIN] and DBG_T[TRGSEL], and DBG_C[BRKEN] and DBG_C[TAG], determine the basic type of debug run as shown in the following table. Some of the 16 possible combinations are not used (refer to the notes at the end of the table). Table 24-18.
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Chapter 24 Debug module (DBG) 24.4.5 FIFO The FIFO is an eight word deep FIFO. In all trigger modes except for event only, the data stored in the FIFO will be change of flow addresses. In the event only trigger modes only the data bus value corresponding to the event is stored. In event only trigger modes, the high byte of the valid data from the FIFO will always read a 0x00. 24.4.5.
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Functional description 24.4.5.4 Reading data from FIFO The data stored in the FIFO can be read using BDM commands provided the DBG module is enabled and not armed (DBG_C[DBGEN] = 1 and DBG_C[ARM] = 0). The FIFO data is read out first-in-first-out. By reading the DBG_CNT[CNT] bits at the end of a trace run, the number of valid words can be determined. The FIFO data is read by optionally reading the DBG_FH register followed by the DBG_FL register.
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Chapter 24 Debug module (DBG) the change of flow event. Because the system is configured for begin-trigger, the DBG remains armed and does not break until the FIFO has been filled by subsequent change of flow events. 24.5 Resets The DBG module cannot cause an MCU reset. There are two different ways this module will respond to reset depending upon the conditions before the reset event.
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Resets MC9S08PA60 Reference Manual, Rev. 1, 9/2012 638 Freescale Semiconductor, Inc.
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How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.