Datasheet

NOTE
The FCLKDIV register must not be written while a flash
command is executing (NVM_FSTAT[CCIF] = 0)
Address: 3020h base + 0h offset = 3020h
Bit 7 6 5 4 3 2 1 0
Read FDIVLD
FDIVLCK FDIV
Write
Reset
0 0 0 0 0 0 0 0
NVM_FCLKDIV field descriptions
Field Description
7
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written since the last reset.
1 FCLKDIV register has been written since the last reset.
6
FDIVLCK
Clock Divider Locked
0 FDIV field is open for writing.
1 FDIV value is locked and cannot be changed. After the lock bit is set high, only reset can clear this bit
and restore writability to the FDIV field in user mode.
5–0
FDIV
Clock Divider Bits
FDIV[5:0] must be set to effectively divide BUSCLK down to 1MHz to control timed events during flash
program and erase algorithms. Refer to the table in the Writing the FCLKDIV register for the
recommended values of FDIV based on the BUSCLK frequency.
4.6.2 Flash Security Register (NVM_FSEC)
The FSEC register holds all bits associated with the security of the MCU and NVM
module. All bits in the FSEC register are readable but not writable. During the reset
sequence, the FSEC register is loaded with the contents of the flash security byte in the
flash configuration field at global address 0xFF7F located in flash memory.
See Security for security function.
Address: 3020h base + 1h offset = 3021h
Bit 7 6 5 4 3 2 1 0
Read KEYEN Reserved SEC
Write
Reset
x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
Flash and EEPROM registers descriptions
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
106 Freescale Semiconductor, Inc.