Datasheet

4.6.5 Flash Error Configuration Register (NVM_FERCNFG)
The FERCNFG register enables the flash error interrupts for the FERSTAT flags.
Address: 3020h base + 5h offset = 3025h
Bit 7 6 5 4 3 2 1 0
Read 0
DFDIE SFDIE
Write
Reset
0 0 0 0 0 0 0 0
NVM_FERCNFG field descriptions
Field Description
7–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
DFDIE
Double Bit Fault Detect Interrupt Enable
The DFDIE bit controls interrupt generation when a double bit fault is detected during a flash block read
operation.
0 DFDIF interrupt disabled.
1 An interrupt will be requested whenever the DFDIF flag is set.
0
SFDIE
Single Bit Fault Detect Interrupt Enable
The SFDIE bit controls interrupt generation when a single bit fault is detected during a flash block read
operation.
0 SFDIF interrupt disabled whenever the SFDIF flag is set.
1 An interrupt will be requested whenever the SFDIF flag is set.
4.6.6 Flash Status Register (NVM_FSTAT)
The FSTAT register reports the operational status of the flash and EEPROM module.
Address: 3020h base + 6h offset = 3026h
Bit 7 6 5 4 3 2 1 0
Read
CCIF
0
ACCERR FPVIOL
MGBUSY 0 MGSTAT
Write
Reset
1 0 0 0 0 0 0 0
NVM_FSTAT field descriptions
Field Description
7
CCIF
Command Complete Interrupt Flag
The CCIF flag indicates that a flash command has completed. The CCIF flag is cleared by writing a 1 to
CCIF to launch a command and CCIF will stay low until command completion or command violation.
Table continues on the next page...
Chapter 4 Memory map
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 109