Datasheet

NVM_FERSTAT field descriptions
Field Description
7–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
DFDIF
Double Bit Fault Detect Interrupt Flag
The setting of the DFDIF flag indicates that a double bit fault was detected in the stored parity and data
bits during a flash array read operation or that a flash array read operation returning invalid data was
attempted on a flash block that was under a flash command operation. The DFDIF flag is cleared by
writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.
NOTE: The single bit fault and double bit fault flags are mutually exclusive for parity errors, meaning that
an ECC fault occurrence can be either single fault or double fault but never both. A simultaneous
access collision, when the flash array read operation is returning invalid data attempted while a
command is running, is indicated when both SFDIF and DFDIF flags are high.
NOTE: There is a one cycle delay in storing the ECC DFDIF and SFDIF fault flags in the register. At least
one NOP is required after a flash memory read before checking FERSTAT for the occurrence of
EEC errors.
0 No double bit fault detected.
1 Double bit fault detected or a flash array read operation returning invalid data was attempted while
command running.
0
SFDIF
Single Bit Fault Detect Interrupt Flag
With the IGNSF bit in the FCNFG register clear, the SFDIF flag indicates that a single bit fault was
detected in the stored parity and data bits during a flash array read operation or that a flash array read
operation returning invalid data was attempted on a flash block that was under a flash command
operation. The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on
SRFDIF.
0 No single bit fault detected.
1 Single bit fault detected and corrected or a flash array read operation returning invalid data was
attempted while command running.
4.6.8 Flash Protection Register (NVM_FPROT)
The FPROT register defines which flash sectors are protected against program and erase
operations.
The unreserved bits of the FPROT register are writable with the restriction that the size of
the protected region can only be increased (see Protection).
During the reset sequence, the FPROT register is loaded with the contents of the flash
protection byte in the flash configuration field at global address 0xFF7C located in flash
memory. To change the flash protection that will be loaded during the reset sequence, the
upper sector of the flash memory must be unprotected, then the flash protection byte must
be reprogrammed.
Chapter 4 Memory map
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 111