Datasheet

entry to the ISR. In rare cases, the I bit may be cleared inside an ISR, after clearing the
status flag that generated the interrupt, so that other interrupts can be serviced without
waiting for the first service routine to finish. This practice is recommended only for the
most experienced programmers because it can lead to subtle program errors that are
difficult to debug.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction that
restores the CCR, A, X, and PC registers to their pre-interrupt values by reading the
previously saved information off the stack.
Note
For compatibility with the M68HC08, the H register is not
automatically saved and restored. Push H onto the stack at the
start of the interrupt service routine (ISR) and restore it
immediately before the RTI that is used to return from the ISR.
When two or more interrupts are pending when the I bit is cleared, the highest priority
source is serviced first.
5.1.1 Interrupt stack frame
The following figure shows the contents and organization of a stack frame. Before the
interrupt, the stack pointer (SP) points at the next available byte location on the stack.
The current values of CPU registers are stored on the stack, starting with the low-order
byte of the program counter (PC) and ending with the CCR. After stacking, the SP points
at the next available location on the stack, which is the address that is one less than the
address where the CCR was saved. The PC value that is stacked is the address of the
instruction in the main program that would have executed next if the interrupt had not
occurred.
Interrupts
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
118 Freescale Semiconductor, Inc.