Datasheet

* High byte (H) of index register is not automatically stacked.
STACKING
ORDER
7
5
5
4
4
3
3
*
1
1
2
2
0
UNSTACKING
ORDER
PROGRAM COUNTER LOW
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER (LOW BYTE X)
PROGRAM COUNTER HIGH
TOWARD LOWER ADDRESSES
TOWARD HIGHER ADDRESSES
SP BEFORE
SP AFTER
INTERRUPT STACKING
THE INTERRUPT
Figure 5-1. Interrupt stack frame
When an RTI instruction executes, these values are recovered from the stack in reverse
order. As part of the RTI sequence, the CPU fills the instruction pipeline by reading three
bytes of program information, starting from the PC address recovered from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning
from the ISR. Typically, the flag must be cleared at the beginning of the ISR because if
another interrupt is generated by this source it will be registered so that it can be serviced
after completion of the current ISR.
5.1.2 Interrupt vectors, sources, and local masks
The following table provides a summary of all interrupt sources. High-priority sources
are located toward the bottom of the table. The high-order byte of the address for the
interrupt service routine is located at the first address in the vector address column, and
the low-order byte of the address for the interrupt service routine is located at the next
higher address.
When an interrupt condition occurs, an associated flag bit is set. If the associated local
interrupt enable is 1, an interrupt request is sent to the CPU. If the global interrupt mask
(I bit in the CCR) is 0, the CPU finishes the current instruction, stacks the PCL, PCH, X,
A, and CCR CPU registers, sets the I bit, and then fetches the interrupt vector for the
highest priority pending interrupt. Processing then continues in the interrupt service
routine.
Chapter 5 Interrupt
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 119