Datasheet

DECODE
VFETCH
INTOUT0
INTIN0
ILR0[1:0]
ILR47
CPU
ILR0
ILR Register Content
IPM
ADDRESS[5:0]
IPMPS
[1
:
0]
[1:0]
[1:0]
[1:0]
[1:0]
INTOUT1
INTIN1
ILR1[1:0]
v
v
v
INTOUT47
INTIN47
ILR47[1:0]
IPCE
x
x
x
x
x
x
x x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
xx
x
x
x
x
Two bits are pushed during vector fetch
software (PULIPM = 1)
Two bits are pulled by
.
.
.
LOGIC
6
AND SHIFT
(Interrupt Priority Mask Pseudo Stack Register)
+
+
+
.
.
. .
.
.
. .
.
.
. .
Inputs
Outputs
(IPC Enable)
00
1
0
Stop
Figure 5-2. Interrupt priority controller block diagram
The IPC works with the existing HCS08 interrupt mechanism to allow nested interrupts
with programmable priority levels. This module also allows implementation of
preemptive interrupt according to the programmed interrupt priority with minimal
software overhead. The IPC consists of three major functional blocks:
• The interrupt priority level registers
• The interrupt priority level comparator set
• The interrupt mask register update and restore mechanism
Chapter 5 Interrupt
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 121