Datasheet

IRQ_SC field descriptions (continued)
Field Description
1
IRQIE
IRQ Interrupt Enable
This read/write control bit determines whether IRQ events generate an interrupt request.
0 Interrupt request when IRQF set is disabled (use polling).
1 Interrupt requested whenever IRQF = 1.
0
IRQMOD
IRQ Detection Mode
This read/write control bit selects either edge-only detection or edge-and-level detection.
0 IRQ event on falling/rising edges only.
1 IRQ event on falling/rising edges and low/high levels.
Interrupt priority control register
IPC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
3E IPC Status and Control Register (IPC_SC) 8 R/W 20h 5.4.1/128
3F Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS) 8 R 00h 5.4.2/129
3050 Interrupt Level Setting Registers n (IPC_ILRS0) 8 R/W 00h 5.4.3/129
3051 Interrupt Level Setting Registers n (IPC_ILRS1) 8 R/W 00h 5.4.3/129
3052 Interrupt Level Setting Registers n (IPC_ILRS2) 8 R/W 00h 5.4.3/129
3053 Interrupt Level Setting Registers n (IPC_ILRS3) 8 R/W 00h 5.4.3/129
3054 Interrupt Level Setting Registers n (IPC_ILRS4) 8 R/W 00h 5.4.3/129
3055 Interrupt Level Setting Registers n (IPC_ILRS5) 8 R/W 00h 5.4.3/129
3056 Interrupt Level Setting Registers n (IPC_ILRS6) 8 R/W 00h 5.4.3/129
3057 Interrupt Level Setting Registers n (IPC_ILRS7) 8 R/W 00h 5.4.3/129
3058 Interrupt Level Setting Registers n (IPC_ILRS8) 8 R/W 00h 5.4.3/129
3059 Interrupt Level Setting Registers n (IPC_ILRS9) 8 R/W 00h 5.4.3/129
5.4
Chapter 5 Interrupt
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 127