Datasheet

IPC_SC field descriptions (continued)
Field Description
IPMPS register. Writing IPM with PULIPM setting when IPCE is already set, the IPM will restore the value
pulled from the IPMPS register, not the value written to the IPM register.
5.4.2 Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)
This register is used to store the previous interrupt priority mask level temporarily when
the currently active interrupt is executed.
Address: 3Eh base + 1h offset = 3Fh
Bit 7 6 5 4 3 2 1 0
Read IPM3 IPM2 IPM1 IPM0
Write
Reset
0 0 0 0 0 0 0 0
IPC_IPMPS field descriptions
Field Description
7–6
IPM3
Interrupt Priority Mask pseudo stack position 3
This field is the pseudo stack register for IPM3. The most recent information is stored in IPM3.
5–4
IPM2
Interrupt Priority Mask pseudo stack position 2
This field is the pseudo stack register for IPM2. The most recent information is stored in IPM2.
3–2
IPM1
Interrupt Priority Mask pseudo stack position 1
This field is the pseudo stack register for IPM1. The most recent information is stored in IPM1.
1–0
IPM0
Interrupt Priority Mask pseudo stack position 0
This field is the pseudo stack register for IPM0. The most recent information is stored in IPM0.
5.4.3 Interrupt Level Setting Registers n (IPC_ILRSn)
This set of registers (ILRS0-ILRS9) contains the user specified interrupt level for each
interrupt source, and indicates the number of the register (ILRSn is ILRS0 through
ILRS9).
Address: 3Eh base + 3012h offset + (1d × i), where i=0d to 9d
Bit 7 6 5 4 3 2 1 0
Read
ILRn3 ILRn2 ILRn1 ILRn0
Write
Reset
0 0 0 0 0 0 0 0
Chapter 5 Interrupt
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 129