Datasheet

• Background debug forced reset
• External reset pin (RESET)
• Internal clock source module reset (CLK)
Each of these sources, with the exception of the background debug forced reset, has an
associated bit in the system reset status (SRS) register.
System options
6.4.1 BKGD pin enable
After POR, PTA4/ACMPO/BKGD/MS pin functions as BKGD output. The
SYS_SOPT1[BKGDPE] bit must be set to enable the background debug mode pin enable
function. When this bit is clear, this pin can function as PTA4 or ACMP output.
6.4.2 RESET pin enable
After POR reset, PTA5/IRQ/TCLK0/RESET functions as RESET. The
SYS_SOPT1[RSTPE] bit must be set to enable the other functions. When this bit is clear,
this pin can function as PTA5, IRQ, or TCLK0.
6.4.3 SCI0 pin reassignment
After reset, SCI0 module pinouts of RxD and TxD are mapped on PTB0 and PTB1,
respectively. SYS_SOPT1[SCI0PS] bit enables to reassign SCI0 pinouts on PTA2 and
PTA3.
6.4.4 SPI0 pin reassignment
After reset, SPI0 module pinouts of SPSCK0, MOSI0, MISO0, and SS0 are mapped on
PTB2, PTB3, PTB4, and PTB5. SYS_SOPT1[SPI0PS] bit enables to reassign the SPI0
pinouts on PTE0, PTE1, PTE2, and PTE3, respectively. Please note PTE1/MOSI0 and
PTE0/SPSCK0 can provide up to 20 mA sink/source current, which is desirable for high-
speed SPI communication.
6.4
System options
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
132 Freescale Semiconductor, Inc.