Datasheet

6.4.5 IIC pins reassignments
After POR reset, IIC module pinouts of SDA and SCL are mapped on PTA2 and PTA3.
SYS_SOPT1[IICPS] bit enables to reassign the IIC pinout pair on PTB6 and PTB7
respectively. Please note the PTA2 and PTA3 operate as true open drain, which can
support different level IIC communication. When PTB6 and PTB7 act as IIC pins, the
remote IIC level is limited to no more than MCU V
DD
.
6.4.6 FTM2 channels pin reassignment
After POR reset, FTM2 channel pinouts of FTM2CH0, FTM2CH1, FTM2CH2, and
FTM2CH3 are default mapped on PTC0, PTC1, PTC2, and PTC3. When set,
SYS_SOPT1[FTM2PS] bit enables to reassignment these FTM2 channels on PTH0,
PTH1, PTD0, and PTD1, respectively. As PTH0, PTH1, PTD0, PTD1, PTB4, and PTB5
can provide up to 20 mA sink/source current, each FTM2 channel can provide high
current with the same time base when this bit is set.
6.4.7 Bus clock output pin enable
The system bus clock can be outputted on PTH2 when the SYS_SOPT3[CLKOE] bits are
set by nonzero. Before mapping on the pinout, the output of bus clock can be pre-divided
by 1, 2, 4, 8, 16, 32, 64, or 128 by setting SYS_SOPT3[BUSREF].
6.5 System interconnection
This device contains a set of system-level logics for module-to-module interconnection
for flexible configuration. These interconnections provide the hardware trigger function
between modules with least software configuration, which is ideal for infrared
communication, serial communication baudrate detection, low-end motor control,
metering clock calibration, and other general-purpose applications.
Chapter 6 System control
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 133