Datasheet

SCI0
txd
rxd
FTM0
ch1
ch0
–
+
RTC
ADC
FTM2
fault0
fault1
fault2
fault3
trigger0
trigger1
trg
ADHWT
RXDCE
ACIC
RXDFE
PTB1/KBI0P5/TxD0/ADP5
RTCC
0
1
1
0
trigger2
FTMSYNC
matchtrg
inittrg
MTIM0
2
N
CLKOE
TXDME
PTH2/BUSOUT
BUSREF
ICSCLK
0
1
DELAY
ovf
FTM1
ch1
ch0
00
01
10
11
ovf
ovf
PTA6/FTM2FAULT1/ADP2
PTA7/FTM2FAULT2/ADP3
PTB0/KBI0P4/RxD0/ADP4
1
Figure 6-1. System interconnection diagram
6.5.1 ACMP output selection
When set, the SYS_SOPT2[ACIC] bit enables the output of ACMP to connect to the
FTM1CH0, the FTM1CH0 pin is released to other shared functions.
6.5.2 SCI0 TxD modulation
SCI0 TXD can be modulated by FTM0 channel 0 output. When SYS_SOPT2[TXDME]
bit is set, the TXD output is passed to an AND gate with FTM0 channel 0 output before
mapping on TXD0 pinout. When this bit is clear, the TXD is directly mapped on the
pinout. To enable IR modulation function, both FTM0CH0 and SCI must be active. The
FTM0 counter modulo register specifies the period of the PWM, and the FTM0 channel 0
value register specifies the duty cycle of the PWM. Then, when TXDME bit is enabled,
each data transmitted via TXD0 from SCI0 is modulated by the FTM0 channel 0 output,
and the FTM0CH0 pin is released to other shared functions.
System interconnection
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
134 Freescale Semiconductor, Inc.