Datasheet

SCI0
TXDME
FTM0CH0
PORT LOGIC
PTB1/KBI0P5/TXD0/ADP5
TXD0
0
1
Figure 6-2. IR modulation diagram
6.5.3 SCI0 RxD capture
RxD0 pin is selectable connected to SCI0 module directly or tagged to FTM0 channel 1.
When SYS_SOPT2[RXDCE] bit is set, the RxD0 pin is connected to both SCI0 and
FTM0 channel 1, and the FTM0CH1 pin is released to other shared functions. When this
bit is clear, the RxD0 pin is connected to SCI0 only.
SCI0
RXDCE
RxD0
RxD0
FTM0 CH1
Figure 6-3. RxD0 capture function diagram
6.5.4 SCI0 RxD filter
When SYS_SOPT2[RXDFE] bit is clear, the RxD0 pin is connected to SCI0 module
directly. When this bit is set, the ACMP output is connected to the receive channel of
SCI0. To enable RxD filter function, both SCI0 and ACMP must be active. If this
function is active, the SCI0 external RxD0 pin is released to other shared functions
regardless of the configuration of SCI0 pin reassignment. When SCI0 RxD capture
function is active, the ACMP output is injected to FTM0CH1 as well.
Chapter 6 System control
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 135