Datasheet

SCI0
0
1
RXDFE
RXD0
+
To SCI0 RxD
Capture Function
From Internal or External
Reference Voltage
ACMP0
ACMP1
Figure 6-4. IR demodulation diagram
6.5.5 RTC capture
RTC overflow may be captured by FTM1 channel 1 by setting SYS_SOPT2[RTCC] bit.
When this bit is set, the RTC overflow is connected to FTM1 channel 1 for capture, the
FTM1CH1 pin is released to other shared functions.
6.5.6 FTM2 software synchronization
FTM2 contains three synchronization input trigger, one of which is a software trigger by
writing 1 to the SYS_SOPT2[FTMSYNC] bit. Writing 0 to this bit takes no effect. This
bit is always read 0.
6.5.7 ADC hardware trigger
ADC module may initiate a conversion via a hardware trigger. MTIM0 overflow, RTC,
FTM2 match trigger with 8-bit programmable delay, and FTM2 init trigger with 8-bit
programmable delay can be enabled as the hardware trigger for the ADC module by
setting the SYS_SOPT2[ADHWT] bits. The following table shows the ADC hardware
trigger setting.
Table 6-1. ADC hardware trigger setting
ADHWT ADC hardware trigger
0:0 RTC overflow
0:1 MTIM0 overflow
1:0 FTM2 init trigger with 8-bit programmable delay
1:1 FTM2 match trigger with 8-bit programmable delay
System interconnection
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
136 Freescale Semiconductor, Inc.