Datasheet

When ADC hardware trigger selects the output of FTM2 triggers, an 8-bit delay block
will be enabled. This logic delays any trigger from FTM2 with an 8-bit counter whose
value is specified by SYS_SOPT4[DELAY] bit. The reference clock to this module is the
output of ICSCLK with selectable pre-divider specified by SYS_SOPT3[BUSREF].
System Control Registers
SYS memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
3000 System Reset Status Register (SYS_SRS) 8 R 82h 6.6.1/137
3001
System Background Debug Force Reset Register
(SYS_SBDFR)
8
W
(always
reads 0)
00h 6.6.2/139
3002 System Device Identification Register: High (SYS_SDIDH) 8 R 00h 6.6.3/140
3003 System Device Identification Register: Low (SYS_SDIDL) 8 R 40h 6.6.4/140
3004 System Options Register 1 (SYS_SOPT1) 8 R/W 0Ch 6.6.5/141
3005 System Options Register 2 (SYS_SOPT2) 8 R/W 00h 6.6.6/142
3006 System Options Register 3 (SYS_SOPT3) 8 R/W 00h 6.6.7/143
3007 System Options Register 4 (SYS_SOPT4) 8 R/W 00h 6.6.8/144
304A Illegal Address Register: High (SYS_ILLAH) 8 R Undefined 6.6.9/145
304B Illegal Address Register: Low (SYS_ILLAL) 8 R Undefined 6.6.10/145
30F8 Universally Unique Identifier Register 1 (SYS_UUID1) 8 R Undefined 6.6.11/146
30F9 Universally Unique Identifier Register 2 (SYS_UUID2) 8 R Undefined 6.6.12/146
30FA Universally Unique Identifier Register 3 (SYS_UUID3) 8 R Undefined 6.6.13/147
30FB Universally Unique Identifier Register 4 (SYS_UUID4) 8 R Undefined 6.6.14/147
30FC Universally Unique Identifier Register 5 (SYS_UUID5) 8 R Undefined 6.6.15/148
30FD Universally Unique Identifier Register 6 (SYS_UUID6) 8 R Undefined 6.6.16/148
30FE Universally Unique Identifier Register 7 (SYS_UUID7) 8 R Undefined 6.6.17/149
30FF Universally Unique Identifier Register 8 (SYS_UUID8) 8 R Undefined 6.6.18/149
6.6.1 System Reset Status Register (SYS_SRS)
This register includes read-only status flags to indicate the source of the most recent
reset. When a debug host forces reset by writing 1 to the SYS_SBDFR[BDFR] bit, none
of the status bits in SRS will be set. The reset state of these bits depends on what caused
the MCU to reset.
NOTE
For PIN, WDOG, and ILOP, any of these reset sources that are
active at the time of reset (not including POR or LVR) will
6.6
Chapter 6 System control
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 137