Datasheet

cause the corresponding bit(s) to be set; bits corresponding to
sources that are not active at the time of reset will be cleared.
NOTE
The RESET values in the figure are values for power on reset;
for other resets, the values depend on the trigger causes.
Address: 3000h base + 0h offset = 3000h
Bit 7 6 5 4 3 2 1 0
Read POR PIN WDOG ILOP 0 LOC LVD 0
Write
Reset
1 0 0 0 0 0 1 0
SYS_SRS field descriptions
Field Description
7
POR
Power-On Reset
Reset was caused by the power-on detection logic. When the internal supply voltage was ramping up at
the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while the
internal supply was below the LVR threshold.
NOTE: This bit POR to 1, LVR to uncertain value and reset to 0 at any other conditions.
0 Reset not caused by POR.
1 POR caused reset.
6
PIN
External Reset Pin
Reset was caused by an active low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
5
WDOG
Watchdog (WDOG)
Reset was caused by the WDOG timer timing out. This reset source may be blocked by WDOGE = 0.
0 Reset not caused by WDOG timeout.
1 Reset caused by WDOG timeout.
4
ILOP
Illegal Opcode
Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP instruction is
considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
LOC
Internal Clock Source Module Reset
Reset was caused by an ICS module reset.
Table continues on the next page...
System Control Registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
138 Freescale Semiconductor, Inc.