Datasheet

SYS_SRS field descriptions (continued)
Field Description
0 Reset not caused by ICS module.
1 Reset caused by ICS module.
1
LVD
Low Voltage Detect
If the LVDRE bit is set in run mode or both LVDRE and LVDSE bits are set in stop mode, and the supply
drops below the LVD trip voltage, an LVD reset will occur. This bit is also set by POR.
NOTE: This bit reset to 1 on POR and LVR and reset to 0 on other reset.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6.6.2 System Background Debug Force Reset Register (SYS_SBDFR)
This register contains a single write-only control bit. A serial background command such
as WRITE_BYTE must be used to write to SYS_SBDFR. Attempts to write this register
from a user program are ignored. Reads always return 0x00.
NOTE
This register is the same as the BDC_SBDFR.
Address: 3000h base + 1h offset = 3001h
Bit 7 6 5 4 3 2 1 0
Read 0 0
Write BDFR
Reset
0 0 0 0 0 0 0 0
SYS_SBDFR field descriptions
Field Description
7–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
BDFR
Background Debug Force Reset
A serial background command such as WRITE_BYTE may be used to allow an external debug host to
force a target system reset. Writing logic 1 to this bit forces an MCU reset. This bit cannot be written from
a user program.
NOTE: BDFR is writable only through serial background debug commands, not from user programs.
Chapter 6 System control
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 139